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Merge pull request #4339 from YosysHQ/mmicko/lib_as_attribute 

verific: expose library name as module attribute
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Miodrag Milanović 2024-04-15 20:25:49 +02:00 committed by GitHub
parent 1527cc84c4 af94123730
commit e78c38b556
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frontends/verific/verific.cc
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@ -1430,6 +1430,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
#ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl()) {
NameSpace name_space(0);