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12789 Commits

Author SHA1 Message Date
github-actions[bot] 8b2a001021 Bump version 2023-06-13 00:17:19 +00:00
Jannis Harder 06f06c7be2
Merge pull request #3801 from jix/witness-aiw2yw-xbits 2023-06-12 16:12:39 +02:00
Miodrag Milanović a310bd2d23
Merge pull request #3802 from YosysHQ/micko/build_full 
Improve Verific usage in plugins
 2023-06-12 16:07:06 +02:00
Miodrag Milanović 8b74e8ad3a
Merge pull request #3796 from YosysHQ/micko/update_abc 
Update ABC to latest
 2023-06-12 16:06:56 +02:00
Miodrag Milanovic 34a6bef768 link verific where appropriate and link full archives 2023-06-12 10:01:35 +02:00
Miodrag Milanovic 75cf79588e Add ability for user plugin to add new verific log callback 2023-06-12 10:01:01 +02:00
Jannis Harder dcc4d6e90b yosys-witness: Don't treat aiw x-bits as don't change 
While treating initialization only bits as don't change during later
cycles is correct, actual x-bits should be kept as x-bits.
 2023-06-09 15:21:22 +02:00
N. Engelhardt 236e15f3b0
Merge pull request #3783 from YosysHQ/krys/docs 2023-06-09 15:13:42 +02:00
Miodrag Milanović bac4c55ed6
Merge pull request #3723 from povik/pygen-const 
Fix the python generator for a bunch of const cases
 2023-06-09 15:13:23 +02:00
Miodrag Milanovic e6f7cf3b29 Update tests 2023-06-09 14:41:45 +02:00
github-actions[bot] 5813809ad9 Bump version 2023-06-07 00:17:31 +00:00
Miodrag Milanovic 0d4a670267 Update ABC 2023-06-06 14:37:14 +02:00
Miodrag Milanovic b623888f6a Update ABC to latest 2023-06-06 11:57:20 +02:00
Miodrag Milanovic c5e4eec3ba Next dev cycle 2023-06-06 09:41:26 +02:00
Miodrag Milanovic f7a8284c7b Release version 0.30 2023-06-06 09:38:46 +02:00
github-actions[bot] 73badeccef Bump version 2023-06-06 00:17:35 +00:00
Miodrag Milanović 8cb3bab479
Merge pull request #3792 from pu-cc/gatemate-bram-updates 
gatemate: CC_FIFO_40K simulation model and SDP read behavior fix
 2023-06-05 20:09:03 +02:00
Patrick Urban 61387d78b7 gatemate: Prevent implicit declaration of `ram_{we,en}` 2023-06-05 19:08:44 +02:00
Miodrag Milanović 62fc118548
Merge pull request #3790 from zeldin/makefile-posix-test 
Fix use of non-POSIX test expressions in Makefile
 2023-06-05 16:21:11 +02:00
N. Engelhardt 7c606bd5a3
Merge pull request #3791 from nakengelhardt/nak/show_attr_wires 2023-06-05 16:18:54 +02:00
N. Engelhardt 6f5d984bdb
Merge pull request #3778 from jix/yw_clk2fflogic 2023-06-05 16:15:04 +02:00
github-actions[bot] 88c849d112 Bump version 2023-06-04 00:19:27 +00:00
Claire Xenia Wolf d7f25165a5 Add ninitff line to aiger .aim files 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2023-06-03 14:38:22 +02:00
N. Engelhardt 0707b911c7 show: add -viewer none option 2023-06-01 11:00:07 +02:00
N. Engelhardt 4b986c9c65 fix wire color after BUF 2023-05-31 17:38:46 +02:00
Patrick Urban 2004a9ff4a gatemate: Add CC_FIFO_40K simulation model 2023-05-30 09:06:23 +02:00
Patrick Urban c244a7161b gatemate: Fix SDP read behavior 2023-05-30 09:05:43 +02:00
github-actions[bot] 43b807fe6f Bump version 2023-05-30 00:17:12 +00:00
Marcus Comstedt 1cd1e57e3c Fix use of non-POSIX test expressions in Makefile 
POSIX test only allows "=" for string comparison.  Accepting "==" as
an alias is a bashism.  Even the bash manpage discourages its use.
 2023-05-29 16:53:50 +02:00
Lofty fb7af093a8 intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
N. Engelhardt 26555a998d show -colorattr: extend colors to arrows when wires have attribute 2023-05-26 17:18:21 +02:00
github-actions[bot] 8596c5ce49 Bump version 2023-05-26 00:15:52 +00:00
Krystine Sherwin 3aee765793
Initial version of memory mapping doc 2023-05-26 09:36:01 +12:00
Lofty cac1bc6fbe intel_alm: enable M10K initialisation 2023-05-25 18:56:34 +01:00
Eddie Hung ec8d7b1c68 abc9_ops -prep_hier to unmap entire module 2023-05-25 18:42:08 +01:00
Eddie Hung 862631d657 Add ABC9 DSP cascade test 2023-05-25 18:42:08 +01:00
Lofty 00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
Jannis Harder e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses 
This makes clk2fflogic add an attr to $ff cells that carry the state of
the emulated async FF. The $ff output doesn't have any async updates
that happened in the current cycle, but the $ff input does, so the $ff
input corresponds to the async FF's output in the original design.

Hence this patch also makes the following changes to passes besides
clk2fflogic (but only for FFs with the clk2fflogic attr set):

  * opt_clean treats the input as a register name (instead of the
    output)

  * rename -witness ensures that the input has a public name

  * the formal backends (smt2, btor, aiger) will use the input's
    name for the initial state of the FF in witness files

  * when sim reads a yw witness that assigns an initial value to the
    input signal, the state update is redirected to the output

This ensures that yosys witness files for clk2fflogic designs have
useful and stable public signal names. It also makes it possible to
simulate a clk2fflogic witness on the original design (with some
limitations when the original design is already using $ff cells).

It might seem like setting the output of a clk2fflogic FF to update the
input's initial value might not work in general, but it works fine for
these reasons:

  * Witnesses for FFs are only present in the initial cycle, so we do
    not care about any later cycles.

  * The logic that clk2fflogic generates loops the output of the
    genreated FF back to the input, with muxes in between to apply any
    edge or level sensitive updates. So when there are no active updates
    in the current gclk cycle, there is a combinational path from the
    output back to the input.

  * The logic clk2fflogic generates makes sure that an edge sensitive
    update cannot be active in the first cycle (i.e. the past initial
    value is assumed to be whatever it needs to be to avoid an edge).

  * When a level sensitive update is active in the first gclk cycle, it
    is actively driving the output for the whole gclk cycle, so ignoring
    any witness initialization is the correct behavior.
 2023-05-25 12:48:02 +02:00
Jannis Harder 7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization 2023-05-25 12:46:16 +02:00
gatecat 52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
github-actions[bot] 57c9eb70fe Bump version 2023-05-24 00:15:32 +00:00
Miodrag Milanović 5e36effe3c
Merge pull request #3777 from YosysHQ/micko/vhdl_verific 
Fix importing parametrized VHDL entity
 2023-05-23 11:44:49 +02:00
Miodrag Milanovic ecd289c100 Fix importing parametrized VHDL entity 2023-05-23 08:25:08 +02:00
Jannis Harder 4f3d1be96a
Merge pull request #3767 from YosysHQ/krys/yw_fix 
Assign wires an smtoffset
 2023-05-22 16:10:55 +02:00
Jannis Harder 5fb1223861
Merge pull request #3733 from AdamHillier/aiger-inputs 
Add outputs before inputs to the sigmap in the AIGER backend.
 2023-05-22 16:09:15 +02:00
N. Engelhardt 890849447f
Merge pull request #3716 from antmicro/kr/brackets 2023-05-22 16:06:38 +02:00
github-actions[bot] cdeef5481c Bump version 2023-05-22 00:16:53 +00:00
Krystine Sherwin 18b44a1e84
yosys-witness: add append option to yw2yw 
Can now append a user defined number of steps to input traces when joining.
If the number of steps is +ve, inputs are all set to 0.
If -ve then steps are skipped.
If all of steps are skipped (including init step) then the input trace will not be copied.
If more than one input trace is provided, the append option will need to be provided the same number of times as there are input traces.
 2023-05-22 11:44:19 +12:00
Krystine Sherwin 8c9a0b51d4
yosys-witness concat yw trace files 
Intended for use with SCY to combine sequential cover traces.
Arbitrary number of inputs, will load all and attempt to join them.  Each trace will be replayed one after the other, in the same order as the files are provided.
Mismatch in init_only fields seems to work fine, with values in subsequent traces being assigned in the initial only if they weren't previously defined.
Uncertain if a mismatch in non init_only fields will cause problems.
Fixes WitnessSig.__eq__().
Adds helper functions to WitnessValues and ReadWitness classes.
 2023-05-22 10:13:17 +12:00
CORRADI Quentin e7156c644d Standard compliance for tests/verilog/block_labels.ys 
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
 2023-05-21 16:38:14 -04:00