Clifford Wolf
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23cf23418c
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Fixed handling of boolean attributes (frontends)
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2013-10-24 11:20:13 +02:00 |
Johann Glaser
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6c4cbc03c2
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Added support for notif0/notif1 primitives
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2013-08-20 11:23:59 +02:00 |
Clifford Wolf
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8656b1c08f
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Added support for bufif0/bufif1 primitives
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2013-08-19 19:50:04 +02:00 |
Clifford Wolf
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4214561890
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Improved ast dumping (ast/verilog frontend)
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2013-08-19 19:49:14 +02:00 |
Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
Clifford Wolf
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59dd02baa2
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Fixes and improvements in AST const folding
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2013-06-10 13:56:03 +02:00 |
Clifford Wolf
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db98a18edb
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Enabled AST/Verilog front-end optimizations per default
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2013-06-10 13:19:04 +02:00 |
Clifford Wolf
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c5ee2b306a
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Merge branch 'bugfix'
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2013-05-16 16:44:45 +02:00 |
Clifford Wolf
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6cc8e848b6
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Fixed synthesis of functions in latched blocks
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2013-05-16 16:44:06 +02:00 |
Clifford Wolf
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161565be10
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
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2013-03-31 11:19:11 +02:00 |
Clifford Wolf
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7a99349de4
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Improvements and bugfixes for generate blocks with local signals
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2013-03-26 11:31:34 +01:00 |
Clifford Wolf
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6a382f2aba
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Fixed handling of unconditional generate blocks
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2013-03-26 09:44:54 +01:00 |
Clifford Wolf
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227520f94d
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Added nosync attribute and some async reset related fixes
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2013-03-25 17:13:14 +01:00 |
Clifford Wolf
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df9753d398
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Added mem2reg option to verilog frontend
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2013-03-24 11:13:32 +01:00 |
Clifford Wolf
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3a5244e913
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Another fix in mem2reg ast simplify logic
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2013-03-24 10:42:08 +01:00 |
Clifford Wolf
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bb3357c027
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Improved mem2reg handling in ast simplifier
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2013-03-24 09:27:01 +01:00 |
Clifford Wolf
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e45d1c8865
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Tiny fixes to verilog parser
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2013-03-23 18:54:31 +01:00 |
Clifford Wolf
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a321a5c412
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
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2013-02-27 09:32:19 +01:00 |
Clifford Wolf
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4f0c2862a0
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Added support for verilog genblock[index].member syntax
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2013-02-26 13:18:22 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |