7 Commits

Author	SHA1	Message	Date
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	7f57bc8385	Improved parsing of large integer constants	2014-06-15 08:48:17 +02:00
Clifford Wolf	0b47d907d3	Fixed handling of unsized constants in verilog frontend	2014-01-24 15:05:24 +01:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	46fbe9d262	Added SAT generator and simple sat_solve command	2013-06-07 13:59:13 +02:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00