Later in the check() code we check the bottom wide_log2 bits on the
address port are zeroed out. If the address port is too narrow, we crash
due to out of bounds access. Explicitly assert the address port is wide
enough, so we don't crash on input such as
read_rtlil <<EOF
module \top
wire input 1 \clk
memory width 8 size 2 \mem
cell $memwr $auto$:1:$8
parameter \PRIORITY 1'0
parameter \CLK_POLARITY 1'1
parameter \CLK_ENABLE 1'1
parameter \MEMID "\\mem"
parameter \ABITS 1'0
parameter \WIDTH 6'010000
connect \DATA 16'0000000000000000
connect \ADDR { }
connect \EN 16'0000000000000000
connect \CLK \clk
end
end
EOF
memory
- FfData now keeps track of the module and underlying cell, if any (so
calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
compilation
- the "flip FF data sense by inserting inverters in front and after"
functionality that zinit uses is moved onto FfData class and beefed up
to have dffsr support, to support more use cases
- *_en is split into *_ce (clock enable) and *_aload (async load aka
latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
FFs with async load
While this helper is already useful to squash sequential initializations
into one in cxxrtl, its main purpose is to squash overlapping masked memory
initializations (when they land) and avoid having to deal with them in
cxxrtl runtime.
Transparency is meaningless for asynchronous ports, so we assume
transparent == false to simplify the code in this case. Likewise,
enable is meaningless, and we assume it is const-1. However,
turns out that nMigen emits the former, and Verilog frontend emits
the latter, so squash these issues when ingesting a $memrd cell.
Fixes#2811.
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return. Handle this case correctly in
the helper and in its users.
When extracting read register from a transparent port that has an
enable, reset, or initial value, the usual trick of putting a register
on the address instead of data doesn't work. In this case, create soft
transparency logic instead.
When transparency masks land, this will also be used to handle ports
that are transparent to only a subset of write ports.
Like wide port support, this is still completely unusable, and support
in various passes will be gradually added later. It also has no support
at all in the cell library, so attempting to create a read port with
a reset or initial value will cause an assert failure for now.
Since the packed cell doesn't actually support wide ports yet, we just
auto-narrow them on emit. The future packed cell will add
RD_WIDE_CONTINUATION and WR_WIDE_CONTINUATION parameters so the
transform will be trivially reversible for proper serialization.
Such ports cannot actually be created or used yet, this just adds the
necessary plumbing in the helper. Subsequent commits will gradually
add wide port support to various yosys passes.
This is going to be used to store arbitrary priority masks in the
future. Right now, it is not supported by our cell library, so the
priority_mask is computed from port order on helper construction,
and discarded when emitted. However, this allows us to already convert
helper-using passes to the new model.
Martin Povišer
Emil J
Marcelina Kościelnicka
Catherine