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4439 Commits

Author SHA1 Message Date
tklam 3c5406c31b Merge branch 'master' of https://github.com/YosysHQ/yosys 2018-10-13 22:52:31 +08:00
Ruben Undheim a36d1701dd Fix build error with clang 2018-10-12 22:14:49 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
David Shah 812538a036 BRAM improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-12 14:22:21 +01:00
David Shah bdfead8c64 ecp5: Adding BRAM maps for all size options 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 17:18:17 +01:00
David Shah 983fb7ff88 ecp5: First BRAM type maps successfully 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:35:19 +01:00
David Shah 2ef1af8b58 ecp5: Script for BRAM IO connections 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:11:00 +01:00
David Shah 346cbbdbdc ecp5: Adding BRAM initialisation and config 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
Clifford Wolf 9850de405a Improve Verific importer blackbox handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-07 19:48:55 +02:00
David Shah 31e22c8b96 ecp5: Add blackbox for DP16KD 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 11:35:59 +01:00
Clifford Wolf ed1f0b2577
Merge pull request #651 from ARandomOWL/stdcells_fix 
Fix IdString M in setup_stdcells()
 2018-10-05 09:59:57 +02:00
Clifford Wolf 115ca57647 Add "write_edif -attrprop" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:41:30 +02:00
Clifford Wolf 257a846113
Merge pull request #654 from mithro/patch-1 
Fix misspelling in issue_template.md
 2018-10-05 09:29:26 +02:00
Clifford Wolf 4b0448fc2c Fix compiler warning in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:26:10 +02:00
Tim Ansell 63d53006cb
Fix misspelling in issue_template.md 
It's been bugging me :-P
 2018-10-04 17:15:30 -07:00
Adrian Wheeldon 1355492c89 Fix IdString M in setup_stdcells() 2018-10-04 15:36:26 +01:00
Clifford Wolf 5f1fea08d5 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-04 11:30:55 +02:00
Clifford Wolf bed6c26a6e
Merge pull request #650 from mithro/patch-1 
xilinx: Adding missing inout IO port to IOBUF
 2018-10-04 11:30:00 +02:00
Tim Ansell ad975fb694
xilinx: Adding missing inout IO port to IOBUF 2018-10-03 16:38:32 -07:00
tklam 27c46d94e3 Merge branch 'master' of https://github.com/YosysHQ/yosys 2018-10-03 21:17:03 +08:00
Clifford Wolf 76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix 
ecp5: Don't map ROMs to DRAM
 2018-10-02 10:00:10 +02:00
Clifford Wolf 0a7751a11b
Merge pull request #646 from tomverbeure/issue594 
Fix for issue 594.
 2018-10-02 09:51:44 +02:00
Tom Verbeure cb214fc01d Fix for issue 594. 2018-10-02 07:44:23 +00:00
Aman Goel 90e0938f9a Update to .smv backend 
Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
 2018-10-01 19:03:10 -04:00
Dan Gisselquist 62424ef3de Add read_verilog $changed support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-01 19:41:35 +02:00
David Shah fcd39e1398 ecp5: Don't map ROMs to DRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:34:41 +01:00
Aman Goel 33cb5e05be
Merge pull request #4 from YosysHQ/master 
Merge with official repo
 2018-10-01 09:09:40 -04:00
Clifford Wolf 4d2917447c Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys 2018-09-30 18:44:07 +02:00
Clifford Wolf 9f9fe94b35 Fix handling of $past 2nd argument in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-30 18:43:35 +02:00
Clifford Wolf ac4000d855 Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys 2018-09-28 17:20:43 +02:00
Clifford Wolf 031824e38c Update to v2 YosysVS template 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-28 17:20:16 +02:00
tklam b86eb3deef fix bug: pass by reference 2018-09-26 17:57:39 +08:00
TK Lam 2b89074240 Fix issue #639 2018-09-26 16:11:45 +08:00
Udi Finkelstein 80a07652f2 Fixed issue #630 by fixing a minor typo in the previous commit 
(as well as a non critical minor code optimization)
 2018-09-25 00:32:57 +03:00
Clifford Wolf 8fde05dfa5 Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-24 20:51:16 +02:00
Clifford Wolf eb452ffb28 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-23 10:32:54 +02:00
Clifford Wolf 9659f7a99e Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc 2018-09-23 10:04:37 +02:00
Clifford Wolf 138ba71264 Update CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-23 09:25:40 +02:00
Miodrag Milanovic 41affeeeb9 added prefix to FDirection constants, fixing windows build 2018-09-21 20:43:49 +02:00
Clifford Wolf 2867bf46a9 Update CHANGLELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-21 16:27:07 +02:00
Clifford Wolf bf189122a8 Update Changelog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-21 13:55:20 +02:00
Clifford Wolf dc77ed1e88
Merge pull request #633 from mmicko/master 
Fix Cygwin build and document needed packages
 2018-09-19 15:08:31 +02:00
Clifford Wolf f1972b6c90
Merge pull request #631 from acw1251/master 
Fixed typo in "verilog_write" help message
 2018-09-19 15:07:28 +02:00
Miodrag Milanovic c5e9034834 Fix Cygwin build and document needed packages 2018-09-19 10:16:53 +02:00
acw1251 efac8a45a6 Fixed typo in "verilog_write" help message 2018-09-18 13:34:30 -04:00
Udi Finkelstein c693f595c5 Merge branch 'master' into pr_reg_wire_error 2018-09-18 01:27:01 +03:00
Udi Finkelstein f6fe73b31f Fixed remaining cases where we check fo wire reg/wire incorrect assignments 
on Yosys-generated assignments.
In this case, offending code was:

module top(input in, output out);
function func;
  input arg;
  func = arg;
endfunction
assign out = func(in);
endmodule
 2018-09-18 01:23:40 +03:00
Clifford Wolf 592a82c0ad
Merge pull request #625 from aman-goel/master 
Minor revision to -expose in setundef pass
 2018-09-14 12:36:13 +02:00