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12116 Commits

Author SHA1 Message Date
N. Engelhardt 417fadbefd
Merge pull request #3625 from povik/show_cleanup 2023-02-06 16:11:26 +01:00
github-actions[bot] 45edc8eb98 Bump version 2023-02-05 00:18:39 +00:00
Catherine 5fa96ccdee
Merge pull request #3659 from whitequark/update-abc 
Bump ABCREV to fix WASM build
 2023-02-04 04:09:55 +00:00
Catherine 3af3cc15b5 Bump ABCREV to fix WASM build. 2023-02-04 03:35:53 +00:00
github-actions[bot] 54bf15a5b8 Bump version 2023-02-04 00:16:33 +00:00
Aki Van Ness a90f940615 backends/firrtl: Ensure `modInstance` is valid 
This should fix #3648 where when calling `emit_elaborated_extmodules` it
checks to see if a module is a black-box, however there was no
validation that the cell type was actually known, and it just always
assumed that we would get a valid instance, causing a segfault.
 2023-02-03 08:27:52 -05:00
github-actions[bot] 221036c5b6 Bump version 2023-02-02 00:17:21 +00:00
Jannis Harder 0f2cb80a26
Merge pull request #3655 from jix/smt2_fix_b_op_width 
smt2: Fix operation width computation for boolean producing cells
 2023-02-01 18:06:59 +01:00
Jannis Harder 5e82638408 smt2: Fix operation width computation for boolean producing cells 
The output width for the boolean value should not influence the
operation width. The previous incorrect width extension would still
produce correct results, but could produce invalid smt2 output for
reduction operators when the output width was larger than the width of
the vector to which the reduction was applied.

This fixes #3654
 2023-02-01 12:34:35 +01:00
github-actions[bot] f7c1e4aadf Bump version 2023-01-31 00:17:36 +00:00
Jannis Harder c235802f4a
Merge pull request #3650 from jix/rtlil_roundtrip_z_bits 
backends/rtlil: Do not shorten a value with z bits to 'x
 2023-01-30 16:14:24 +01:00
N. Engelhardt 419f91a2b9 add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
N. Engelhardt ecfa7e9fbc add pmux option to bmuxmap for better fsm detection with verific frontend 2023-01-30 16:12:53 +01:00
github-actions[bot] d11cb6901f Bump version 2023-01-30 00:14:47 +00:00
Dag Lem 26db5a11d3 Resolve struct member package types 2023-01-29 13:51:44 -05:00
Dag Lem db13c6df2b
Handle struct members of union type (#3641) 2023-01-29 13:45:45 -05:00
Jannis Harder b08a880704 backends/rtlil: Do not shorten a value with z bits to 'x 2023-01-29 14:02:25 +01:00
github-actions[bot] 541fdffff2 Bump version 2023-01-26 00:16:37 +00:00
Miodrag Milanović b9155a574e
Merge pull request #3647 from jix/formalff-hierarchy-fix 
formalff: Fix crash with _NOT_ gates in -hierarchy mode
 2023-01-25 13:37:44 +01:00
Jannis Harder afac3f2c76 formalff: Fix crash with _NOT_ gates in -hierarchy mode 2023-01-25 12:55:29 +01:00
github-actions[bot] 755b753e1a Bump version 2023-01-24 00:16:28 +00:00
Miodrag Milanović 8180cc4325
Merge pull request #3624 from jix/sim_yw 
Changes to support SBY trace generation with the sim command
 2023-01-23 16:55:17 +01:00
Miodrag Milanović 245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes 
Fixes for some of clang scan-build detected issues
 2023-01-23 16:24:22 +01:00
Miodrag Milanović 9bc9121b9e
Merge pull request #3636 from YosysHQ/log_plugin 
Call yosys_shutdown to properly cleanup plugins and tcl when expecting error
 2023-01-23 16:24:03 +01:00
gatecat bfacaddca8 show: Remove left-in debug log_warning 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-23 13:54:07 +01:00
Miodrag Milanovic 200ffdccc5 Call yosys_shutdown to properly cleanup plugins and tcl when expecting error 2023-01-20 16:09:42 +01:00
Miodrag Milanović 611f71c670
Merge pull request #3630 from yrabbit/gw1n4c-pll 
gowin: add a new type of PLL - PLLVR
 2023-01-18 08:30:29 +01:00
github-actions[bot] 29e7756b0c Bump version 2023-01-18 00:17:17 +00:00
Claire Xenia Wolf bfc3c20cfb Improve splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2023-01-18 00:31:29 +01:00
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Martin Povišer f9e30ee5e0 passes: show: s/pos/bitpos/ for readability 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 314b864205 passes: show: Reuse string parts in generation of portboxes 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 61abca10a3 passes: show: Touch chunk iteration in gen_portbox 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 60318a5cd8 passes: show: Label no_signode flag 
Label the flag and rearrange the control flow a bit.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 8b1f5fba62 passes: show: Simplify wire bit range logic 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer ad149cc42a passes: show: Factor out 'join_label_pieces' 
In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 5848790835 passes: show: Label signed_suffix flag 
To make it easier to follow what's going on.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 13700e12e5 passes: show: s/idx/dot_idx/ for readability 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer e3709ce776 passes: show: Fix portbox bit ranges in case of driven signals 
When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.

So, taking for example the following Verilog snippet,

  module DRIVER (Q);
     output [7:0] Q;
     assign Q = 8'b10101010;
  endmodule

  module main;
     wire w;
     DRIVER driver(.Q({8{w}}));
  endmodule

make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
github-actions[bot] 956c4e485a Bump version 2023-01-12 01:17:55 +00:00
N. Engelhardt 692a0fa33b print filename in liberty log_header 2023-01-11 21:31:46 +01:00
Jannis Harder d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder 7ddec5093f sim: Improvements and fixes for yw cosim 
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
 2023-01-11 18:07:16 +01:00
Jannis Harder 636b9f2705 Support for BTOR witness to Yosys witness conversion 2023-01-11 18:07:16 +01:00
Jannis Harder 3e25e61778 aiger: Use new JSON code for writing aiger witness map files 2023-01-11 18:07:16 +01:00
Jannis Harder 29461ade17 Add json.{h,cc} for pretty printing JSON 
Avoids errors in trailing comma handling, broken indentation and
improper escaping that is common when building JSON by manually
concatenating strings.
 2023-01-11 18:07:16 +01:00
Jannis Harder dda972a148 sim: New -append option for Yosys witness cosim 
This is needed to support SBY's append option.
 2023-01-11 18:07:16 +01:00
Jannis Harder 2dd5652215 sim: Add Yosys witness (.yw) cosimulation 2023-01-11 18:07:16 +01:00
Jannis Harder 1494cfff00 New kernel/yw.{h,cc} to support reading Yosys witness files 
This contains parsing code as well as generic routines to associate the
hierarchical signals paths within a Yosys witness file to a loaded RTLIL
design, including support for memories.
 2023-01-11 18:07:16 +01:00
Jannis Harder f6458bab70 sim: Only check formal cells during gclk simulation updates 
This is required for compatibility with non-multiclock formal semantics.
 2023-01-11 18:07:16 +01:00