Eddie Hung
283e33ba5a
Trim off leading 1'bx in A
2019-05-02 16:02:37 -07:00
Eddie Hung
fc72f07efd
Add don't care optimisation
2019-05-02 15:01:37 -07:00
Eddie Hung
d80445e049
Use new peepopt from #969
2019-05-02 11:35:57 -07:00
Eddie Hung
8829cba901
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
2019-05-02 11:25:34 -07:00
Eddie Hung
95867109ea
Revert to pre-muxcover approach
2019-05-02 11:25:10 -07:00
Eddie Hung
d05ac7257e
Missing help_mode
2019-05-02 11:14:28 -07:00
Eddie Hung
3b5e8c86a4
Fix -nocarry
2019-05-02 11:00:49 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Clifford Wolf
98925f6c4b
Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine
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Revert synth_xilinx 'fine' label more to how it used to be...
2019-05-02 09:11:07 +02:00
Eddie Hung
485bf372e7
Merge pull request #978 from ucb-bar/fmtfirrtl
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Re-indent firrtl.cc:struct memory - no functional change.
2019-05-01 18:24:21 -07:00
Eddie Hung
d394b9301b
Back to passing all xc7srl tests!
2019-05-01 18:23:21 -07:00
Eddie Hung
31ff0d8ef5
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
2019-05-01 18:09:38 -07:00
Eddie Hung
f86d153cef
Merge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 16:26:43 -07:00
Jim Lawson
6ea09caf01
Re-indent firrtl.cc:struct memory - no functional change.
2019-05-01 16:21:13 -07:00
Clifford Wolf
7a0af004a0
Merge branch 'clifford/fix883'
2019-05-02 00:04:12 +02:00
Clifford Wolf
521663f09e
Add missing enable_undef to "sat -tempinduct-def", fixes #883
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-02 00:03:31 +02:00
Clifford Wolf
e8a157b47c
Merge pull request #977 from ucb-bar/fixfirrtlmem
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Fix #938 - Crash occurs in case when use write_firrtl command
2019-05-01 23:47:16 +02:00
Jim Lawson
38f5424f92
Fix #938 - Crash occurs in case when use write_firrtl command
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Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
2019-05-01 13:16:01 -07:00
Clifford Wolf
93b7fd7744
Fix floating point exception in qwp, fixes #923
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 15:06:46 +02:00
Clifford Wolf
32ff37bb5a
Fix segfault in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 22:20:45 +02:00
Clifford Wolf
e35fe1344d
Disabled "final loop assignment" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 20:22:50 +02:00
Clifford Wolf
9c7d23446d
Merge pull request #972 from YosysHQ/clifford/fix968
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Add final loop variable assignment when unrolling for-loops
2019-04-30 18:09:44 +02:00
Clifford Wolf
a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956
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Drive dangling wires with init attr with their init value
2019-04-30 18:08:41 +02:00
Clifford Wolf
5bc4de077a
Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx
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Refactor synth_xilinx to auto-generate doc
2019-04-30 18:07:19 +02:00
Clifford Wolf
d9d50b0b0c
Merge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 17:00:34 +02:00
Clifford Wolf
58e991a0eb
Merge pull request #973 from christian-krieg/feature/python_bindings
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Feature/python bindings cleanup
2019-04-30 15:48:42 +02:00
Clifford Wolf
84f3a796e1
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:37:46 +02:00
Clifford Wolf
9268cd1613
Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:19:10 +02:00
Clifford Wolf
9af825e31e
Add final loop variable assignment when unrolling for-loops, fixes #968
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
Clifford Wolf
9d117eba9d
Add handling of init attributes in "opt_expr -undriven"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 14:46:12 +02:00
Benedikt Tutzer
dc06e3a28b
Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_bindings
2019-04-30 13:22:33 +02:00
Benedikt Tutzer
124a284487
Cleaned up root directory
2019-04-30 13:19:04 +02:00
Clifford Wolf
b515fd2d25
Add peepopt_muldiv, fixes #930
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 11:25:15 +02:00
Clifford Wolf
4306bebe58
pmgen progress
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 10:51:51 +02:00
Clifford Wolf
d2d402e625
Run "peepopt" in generic "synth" pass and "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:10:37 +02:00
Clifford Wolf
bb4f3642de
Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:04:22 +02:00
Clifford Wolf
58238da133
Progress in shiftmul peepopt pattern
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 07:59:39 +02:00
Clifford Wolf
314ff1e4ca
Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef
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Add -undef option to equiv_opt, passed to equiv_induct
2019-04-29 13:54:26 +02:00
Clifford Wolf
8fde245ea2
Merge pull request #967 from olegendo/depfile_esc_spaces
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escape spaces with backslash when writing dep file
2019-04-29 13:48:52 +02:00
Clifford Wolf
ea547bcaa3
Add "peepopt" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:38:56 +02:00
Clifford Wolf
9f792c599d
Add pmgen support for multiple patterns in one matcher
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:02:05 +02:00
Oleg Endo
4f15e7f00f
fix codestyle formatting
2019-04-29 19:20:33 +09:00
Clifford Wolf
32881a989c
Support multiple pmg files (right now just concatenated together)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 12:09:02 +02:00
Oleg Endo
e531fb203a
escape spaces with backslash when writing dep file
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filenames are sparated by spaces in the dep file. if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
2019-04-29 16:13:34 +09:00
Clifford Wolf
754b1ee4b3
Drive dangling wires with init attr with their init value, fixes #956
2019-04-29 08:44:53 +02:00
Eddie Hung
acafcdc94d
Copy with 1'bx padding in $shiftx
2019-04-28 13:04:34 -07:00
Eddie Hung
e97178a888
WIP
2019-04-28 12:51:00 -07:00
Eddie Hung
af840bbc63
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-28 12:36:04 -07:00
Eddie Hung
4aca928033
Fix spacing
2019-04-26 19:46:34 -07:00
Eddie Hung
0f1ba94924
Remove split_shiftx tests
2019-04-26 19:45:47 -07:00