Commit Graph

13039 Commits

Author SHA1 Message Date
Henri Nurmi 79c0bfcb22 cxxrtl: Remove unnecessary length check 2023-12-13 06:08:01 +00:00
Henri Nurmi dbff694e3d cxxrtl: Use the base name of the interface file for the include directive
Prior to this fix, the `CxxrtlBackend` used the entire path for the include
directive when a separated interface file is generated (via the `-header`
option). This commit updates the code to use the base name of the interface
file.

Since the C++11 standard is used by default, we cannot take advantage of
the `std::filesystem` to get the basename.
2023-12-13 06:08:01 +00:00
github-actions[bot] 3ea6bca23e Bump version 2023-12-13 00:16:10 +00:00
Martin Povišer 5837fe8c91
Merge pull request #4067 from povik/cxxrtl-udivmod-fix
cxxrtl: Fix `ctlz`, `udivmod`
2023-12-12 21:22:25 +01:00
Martin Povišer 320e75a3e3
Merge pull request #4065 from daglem/fix-AST_SHIFT-AST_SHIFTX
Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX
2023-12-12 11:47:29 +01:00
Martin Povišer 7bded221a7
Merge pull request #4066 from daglem/dump_vlog-more-ast-nodes
Uncloak array expressions generated by read_verilog -dump_vlog2
2023-12-12 11:30:07 +01:00
Martin Povišer 18d1907fa8 cxxrtl: Assert well-formedness of input to `udivmod` 2023-12-12 10:08:12 +01:00
Martin Povišer 6206a3af30 cxxrtl: Handle case of `Bits < 4` in formatting of values 2023-12-12 09:51:17 +01:00
Martin Povišer c848d98d91 cxxrtl: Fix `udivmod` logic 2023-12-11 22:11:35 +01:00
Martin Povišer bcf5e92389 cxxrtl: Fix `ctlz` implementation 2023-12-11 22:10:51 +01:00
Dag Lem 655921e851 Uncloak array expressions generated by read_verilog -dump_vlog2
Explicit conversion of AST_TO_SIGNED, AST_TO_UNSIGNED, and AST_CAST_SIZE
makes it possible to reason about simplified array expressions.
2023-12-11 19:12:35 +01:00
Dag Lem cda470d63e Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX
The $shift and $shiftx cells perform a left logical shift if the second
operand is negative. This change passes the sign of the second operand
of AST_SHIFT and AST_SHIFTX into $shift and $shiftx cells, respectively.
2023-12-11 18:58:34 +01:00
Jannis Harder cca12d9d9b
Merge pull request #4055 from povik/sim-hier-prints
sim: Print hierarchy for failed assertions
2023-12-11 16:55:36 +01:00
N. Engelhardt 2858c33f68
Merge pull request #4058 from povik/fix-py-example 2023-12-11 16:49:47 +01:00
Jannis Harder fe686e725f
Merge pull request #4062 from povik/iterator-c++17
Remove deprecated `std::iterator`, fix iterator types
2023-12-11 16:44:31 +01:00
github-actions[bot] 373b651d5b Bump version 2023-12-10 00:17:47 +00:00
Merry 0681baae19 cxxrtl: Extract divmod algorithm into value 2023-12-09 19:23:04 +00:00
Merry 99c8143ded cxxrtl: Remove redundant divmod 2023-12-09 19:23:04 +00:00
Martin Povišer 80b8cd19c4 rtlil: Fix value type for iterator over `SigSpec`
When we are iterating over a `SigSpec`, the visited values will be of
type `SigBit` (as is the return type of `operator*()`). Account for that
in the publicly declared types.
2023-12-09 19:01:39 +01:00
Martin Povišer 189064b8da rtlil, hashlib: Remove deprecated `std::iterator` usage
`std::iterator` has been deprecated in C++17. Yosys is being compiled
against the C++11 standard but plugins can opt to compile against a
newer one. To silence some deprecation warnings when those plugins are
being compiled, replace the `std::iterator` inheritance with the
equivalent type declarations.
2023-12-09 19:01:39 +01:00
Martin Povišer e6021b2b48
Merge pull request #4057 from jix/peepopt_shiftmul_right_padding_fix
peepopt: Fix padding for the peepopt_shiftmul_right pattern
2023-12-07 14:56:53 +01:00
Martin Povišer 44c72e5223 python: Fix import in plugin example
When a plugin is being loaded from Python source, the binding will be
available under

    import libyosys

That is unfortunately different from how a self-standing Python program
would import the Yosys interface, which is

    from pyosys import libyosys

Until that is made consistent, at least fix the example to have it
working as is.
2023-12-07 14:32:29 +01:00
github-actions[bot] fb4cbfa735 Bump version 2023-12-07 00:16:21 +00:00
Jannis Harder 7b74caa5db peepopt: Fix padding for the peepopt_shiftmul_right pattern
The previous version could easily generate a large amount of padding
when the constant factor was significantly larger than the width of the
shift data input. This could lead to huge amounts of logic being
generated before then being optimized away at a huge performance and
memory cost.

Additionally and more critically, when the input width was not a
multiple of the constant factor, the input data was padded with 'x bits
to such a multiple before interspersing the 'x padding needed to align
the selectable windows to power-of-two offsets.

Such a final padding would not be correct for shifts besides $shiftx,
and the previous version did attempt to remove that final padding at the
end so that the native zero/sign/x-extension behavior of the shift cell
would be used, but since the last selectable window also got
power-of-two padding appended after the padding the code is trying to
remove got added, it did not actually fully remove it in some cases.

I changed the code to only add 'x padding between selectable windows,
leaving the last selectable window unpadded. This omits the need to add
final padding to a multiple of the constant factor in the first place.
In turn, that means the only 'x bits added are actually impossible to
select. As a side effect no padding is added when the constant factor is
equal to or larger than the width of the shift data input, also solving
the reported performance bug.

This fixes #4056
2023-12-06 18:35:44 +01:00
Martin Povišer 6581b5593c sim: Print hierarchy for failed assertions 2023-12-06 12:09:07 +01:00
Miodrag Milanović 45dd9eca64
Merge pull request #4051 from YosysHQ/wasi_ci
Add WASI CI build
2023-12-06 10:52:13 +01:00
Miodrag Milanovic 6dc62bd013 Fix out of tree build 2023-12-06 09:56:35 +01:00
Miodrag Milanovic 56abf92b85 Add WASI CI build 2023-12-06 09:19:11 +01:00
Miodrag Milanovic d71dd5b9bb Fix out of tree build 2023-12-06 09:11:51 +01:00
github-actions[bot] a530321042 Bump version 2023-12-06 00:16:15 +00:00
Martin Povišer 093f9c7bac
Merge pull request #4053 from povik/pmgen-make
pmgen: Have a single make pattern
2023-12-05 19:56:09 +01:00
Martin Povišer 16ea497d7c pmgen: Have a single make pattern
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
2023-12-05 18:30:13 +01:00
Miodrag Milanovic 0ccff57062 Next dev cycle 2023-12-05 08:58:28 +01:00
Miodrag Milanovic 8f07a0d840 Release version 0.36 2023-12-05 08:55:12 +01:00
github-actions[bot] 2ffea67b04 Bump version 2023-12-05 00:16:14 +00:00
Martin Povišer b1bbb5827a
Merge pull request #4050 from povik/ql-bram_types-gen
quicklogic: Generate `bram_types_sim.v` at build time
2023-12-04 20:04:20 +01:00
Martin Povišer e0fc48e196 quicklogic: Generate `bram_types_sim.v` at build time 2023-12-04 18:21:00 +01:00
Miodrag Milanović 8738143880
Merge pull request #4045 from povik/upstream-ql-k6n10f
Upstream QuickLogic k6n10f flow
2023-12-04 16:47:17 +01:00
Miodrag Milanovic 96fecf0716 Revert "Add attributes to module instantiation"
This reverts commit 8f207eed1b.
2023-12-04 16:37:01 +01:00
Martin Povišer 22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
Krystine Sherwin e5c32f399a synth_quicklogic: Testing double_sync_ram_tdp 2023-12-04 15:52:03 +01:00
Krystine Sherwin 97354782c0 Adding double_sync_ram_tdp to blockram.v 2023-12-04 15:52:03 +01:00
Krystine Sherwin 215a777eb3 qlf_tests: minor adjustment
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 15:52:03 +01:00
N. Engelhardt 33ca6994b7 remove example test 2023-12-04 15:52:03 +01:00
N. Engelhardt 3c5b0ab164 fix test setup for synth_quicklogic memory tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 509d176523 attempting to sim split memory tests
and failing
2023-12-04 15:52:03 +01:00
Krystine Sherwin 0d1668c1ee QLF_TDP36K: asymmetric simulation tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 497cd021af QLF_TDP36K: truncation tests matter
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
2023-12-04 15:52:03 +01:00
Krystine Sherwin 7f12d0ba95 QLF_TDP36K: more basic tdp/sdp sim tests
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-04 15:52:03 +01:00
Krystine Sherwin 3d08ed216d QLF_TDP36K: parameterised sim test gen
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-04 15:52:03 +01:00