mirror of https://github.com/YosysHQ/yosys.git
Uncloak array expressions generated by read_verilog -dump_vlog2
Explicit conversion of AST_TO_SIGNED, AST_TO_UNSIGNED, and AST_CAST_SIZE makes it possible to reason about simplified array expressions.
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@ -658,11 +658,20 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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if (0) { case AST_NEG: txt = "-"; }
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if (0) { case AST_LOGIC_NOT: txt = "!"; }
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if (0) { case AST_SELFSZ: txt = "@selfsz@"; }
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if (0) { case AST_TO_SIGNED: txt = "signed'"; }
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if (0) { case AST_TO_UNSIGNED: txt = "unsigned'"; }
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fprintf(f, "%s(", txt.c_str());
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children[0]->dumpVlog(f, "");
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fprintf(f, ")");
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break;
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case AST_CAST_SIZE:
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children[0]->dumpVlog(f, "");
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fprintf(f, "'(");
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children[1]->dumpVlog(f, "");
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fprintf(f, ")");
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break;
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if (0) { case AST_BIT_AND: txt = "&"; }
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if (0) { case AST_BIT_OR: txt = "|"; }
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if (0) { case AST_BIT_XOR: txt = "^"; }
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