riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,475 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

13475 Commits

Author SHA1 Message Date
Jannis Harder a7bccdfe8d Update ABC version 2023-06-28 11:20:44 +02:00
Jannis Harder 596da3f2a6
Merge pull request #3815 from charlottia/py312-syntax 2023-06-26 16:36:58 +02:00
Jannis Harder 6be5f6449c
Merge pull request #3816 from jix/smtbmc-cover-keepgoing 2023-06-26 16:35:52 +02:00
Jannis Harder b87af9cec0
Merge pull request #3817 from jix/constant_drive_conflict 2023-06-26 16:19:50 +02:00
github-actions[bot] 2310a0ea9a Bump version 2023-06-25 00:21:16 +00:00
Miodrag Milanović 9ba7170919
Merge pull request #3818 from nakengelhardt/nak/verific_import_mem_access_src_loc 
verific: import src attribute on $memrd/$memwr cells
 2023-06-24 10:42:45 +02:00
N. Engelhardt 21686f0d9d verific: import src attribute on $memrd/$memwr cells 2023-06-23 19:41:36 +02:00
Jannis Harder a07f8ac38a check: Also check for conflicts with constant drivers 2023-06-23 18:07:28 +02:00
Jannis Harder f9744fdfcd smtbmc: Make cover mode respect --keep-going 
As cover mode by default stops looking for further traces when an
assertion fails, it should respect --keep-going.
 2023-06-23 10:27:38 +02:00
Charlotte 3f29bdbbc5 smt2: py3.12+: avoid SyntaxWarning. 
Python 3.12 emits a SyntaxWarning when encountering invalid escape
sequences.  They still parse as expected.  Marking these raw produces
the same result without the warnings.
 2023-06-23 14:40:02 +10:00
Miodrag Milanović f9257d3192
Merge pull request #3811 from YosysHQ/micko/defaultvalue 
Use defaultvalue for init values of input ports
 2023-06-22 09:39:45 +02:00
github-actions[bot] 8f7a9a0b66 Bump version 2023-06-22 00:17:44 +00:00
Claire Xen 51e627686a
Merge pull request #3812 from charlottia/iterator-invalidation 
proc_prune: avoid using invalidated iterator
 2023-06-21 14:46:25 +02:00
Miodrag Milanovic aff0065646 Use defaultvalue for init values of input ports 2023-06-21 13:21:34 +02:00
Charlotte 63e4114233 proc_prune: avoid using invalidated iterator 
An `std::vector<T>::reverse_iterator` stores the
`std::vector<T>::iterator` which points to the (forwards-ordered)
*following* item.  Thus while `vec.rbegin()` dereferences to the final
item of `vec`, the iterator it wraps (`vec.rbegin().base()`) is equal to
`vec.end()`.

In the remove case here, we advance `it` (backwards), erasing the item
we just advanced past by grabbing its (pre-increment) base
forward-iterator and subtracting 1.

The iterator maths here is obviously all OK, but the forward-iterator
that `it` wraps post-increment actually points to the item we just
removed.  That iterator was invalidated by the `erase()` call.

That this works anyway is (AFAICT) some combination of luck and/or
promises that aren't part of the C++ spec, but MSVC's debug iterator
support picks this up.

`erase()` returns the new iterator that follows the item just erased,
which happens to be the exact one we want our reverse-iterator to wrap
for the next loop; we get a fresh iterator to the same base, now without
the preceding item.
 2023-06-21 19:53:08 +10:00
N. Engelhardt 941fa70ce1
Merge pull request #3809 from YosysHQ/nak/show_escape 2023-06-21 10:38:32 +02:00
N. Engelhardt f573aebdd3
Merge pull request #3810 from charlottia/docs-celllib-minor 2023-06-21 10:34:59 +02:00
Charlotte 0c0171bd60 docs: RD_DATA is an output, not input 2023-06-21 17:21:04 +10:00
github-actions[bot] 104edb4587 Bump version 2023-06-21 00:17:27 +00:00
Claire Xen 48cafd5ccf
Merge pull request #1489 from YosysHQ/clifford/ediflsbidx 
Add "write_edif -lsbidx"
 2023-06-20 17:58:44 +02:00
N. Engelhardt 9c7f0e7670 show: truncate very long module names 2023-06-20 12:53:56 +02:00
N. Engelhardt 22c9237716 show: escape angle brackets 2023-06-20 11:17:12 +02:00
Clifford Wolf cff3195caa Improve EDIF lib_cell_ports scan 2023-06-20 10:42:05 +02:00
Clifford Wolf fb9e12761b Add "write_edif -lsbidx" 2023-06-20 10:40:15 +02:00
github-actions[bot] 25954715f0 Bump version 2023-06-20 00:16:06 +00:00
Jannis Harder d3ee4eba5b
Merge pull request #3797 from charlottia/one-length-memories 2023-06-19 16:21:06 +02:00
N. Engelhardt 3fa83ca195
Merge pull request #3808 from YosysHQ/krys/docs 2023-06-19 12:12:56 +02:00
Krystine Sherwin d1b86d2fcf
docs: reflow memory map 
Move additional notes up to the top and give it its own section.  Also reformat some paragraphs, and turn some bullet points into paragraphs.
Split supported patterns section into some kind of grouping.
Currently:
- SDP
- single-port RAM
- reset patterns
- asymmetric
- TDP
 2023-06-19 12:05:51 +12:00
Charlotte Connor c9d31c3c87 smt2: abits needs to be at least 1 for BitVec 
BitVecs need a minimum length of 1; we zero-fill any extra bits in the
extend_u0() calls which works perfectly.
 2023-06-13 15:01:45 +10:00
github-actions[bot] 8b2a001021 Bump version 2023-06-13 00:17:19 +00:00
Jannis Harder 06f06c7be2
Merge pull request #3801 from jix/witness-aiw2yw-xbits 2023-06-12 16:12:39 +02:00
Miodrag Milanović a310bd2d23
Merge pull request #3802 from YosysHQ/micko/build_full 
Improve Verific usage in plugins
 2023-06-12 16:07:06 +02:00
Miodrag Milanović 8b74e8ad3a
Merge pull request #3796 from YosysHQ/micko/update_abc 
Update ABC to latest
 2023-06-12 16:06:56 +02:00
Miodrag Milanovic 34a6bef768 link verific where appropriate and link full archives 2023-06-12 10:01:35 +02:00
Miodrag Milanovic 75cf79588e Add ability for user plugin to add new verific log callback 2023-06-12 10:01:01 +02:00
Jannis Harder dcc4d6e90b yosys-witness: Don't treat aiw x-bits as don't change 
While treating initialization only bits as don't change during later
cycles is correct, actual x-bits should be kept as x-bits.
 2023-06-09 15:21:22 +02:00
N. Engelhardt 236e15f3b0
Merge pull request #3783 from YosysHQ/krys/docs 2023-06-09 15:13:42 +02:00
Miodrag Milanović bac4c55ed6
Merge pull request #3723 from povik/pygen-const 
Fix the python generator for a bunch of const cases
 2023-06-09 15:13:23 +02:00
Miodrag Milanovic e6f7cf3b29 Update tests 2023-06-09 14:41:45 +02:00
github-actions[bot] 5813809ad9 Bump version 2023-06-07 00:17:31 +00:00
Miodrag Milanovic 0d4a670267 Update ABC 2023-06-06 14:37:14 +02:00
Miodrag Milanovic b623888f6a Update ABC to latest 2023-06-06 11:57:20 +02:00
Miodrag Milanovic c5e4eec3ba Next dev cycle 2023-06-06 09:41:26 +02:00
Miodrag Milanovic f7a8284c7b Release version 0.30 2023-06-06 09:38:46 +02:00
github-actions[bot] 73badeccef Bump version 2023-06-06 00:17:35 +00:00
Miodrag Milanović 8cb3bab479
Merge pull request #3792 from pu-cc/gatemate-bram-updates 
gatemate: CC_FIFO_40K simulation model and SDP read behavior fix
 2023-06-05 20:09:03 +02:00
Patrick Urban 61387d78b7 gatemate: Prevent implicit declaration of `ram_{we,en}` 2023-06-05 19:08:44 +02:00
Miodrag Milanović 62fc118548
Merge pull request #3790 from zeldin/makefile-posix-test 
Fix use of non-POSIX test expressions in Makefile
 2023-06-05 16:21:11 +02:00
N. Engelhardt 7c606bd5a3
Merge pull request #3791 from nakengelhardt/nak/show_attr_wires 2023-06-05 16:18:54 +02:00
N. Engelhardt 6f5d984bdb
Merge pull request #3778 from jix/yw_clk2fflogic 2023-06-05 16:15:04 +02:00