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1028 Commits

Author SHA1 Message Date
Eddie Hung fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
Clifford Wolf c25c1e742b
Merge pull request #1308 from jakobwenzel/real_params 
Handle real values when deriving ast modules
 2019-08-20 11:37:26 +02:00
Eddie Hung 3f4886e7a3 Fix typo 2019-08-19 10:42:00 -07:00
Jakob Wenzel 24971fda87 handle real values when deriving ast modules 2019-08-19 14:17:36 +02:00
whitequark 101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Clifford Wolf 2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255 
Fix various NDEBUG compiler warnings
 2019-08-17 15:07:16 +02:00
Clifford Wolf 27d59dc055 Fix erroneous ifndef-NDEBUG in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:49:55 +02:00
Eddie Hung 6b156beda1 Remove unused variable 2019-08-16 13:35:39 -07:00
Eddie Hung 847c54088e Change signature of parse_blif to take IdString 2019-08-15 10:26:24 -07:00
Clifford Wolf 0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf 4f81213165
Merge pull request #1261 from YosysHQ/clifford/verific_init 
Automatically prune init attributes in verific front-end
 2019-08-10 09:47:25 +02:00
Eddie Hung 446dcb3ed3 Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro 2019-08-09 09:17:35 -07:00
Eddie Hung 9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung 03ec8d6551 Run "clean" on mapped_mod in its own design 2019-08-07 09:54:27 -07:00
Clifford Wolf 9260e97aa2 Automatically prune init attributes in verific front-end, fixes #1237 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 15:31:49 +02:00
Clifford Wolf 679bc6507f
Merge pull request #1252 from YosysHQ/clifford/fix1231 
Fix handling of functions/tasks without top-level begin-end block
 2019-08-07 12:14:54 +02:00
David Shah dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix 
Improved JSON attr/param encoding
 2019-08-07 10:40:38 +01:00
Eddie Hung ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung a6bc9265fb RTLIL::S{0,1} -> State::S{0,1} 2019-08-06 16:23:37 -07:00
Eddie Hung 046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Clifford Wolf f1f5b4e375 Fix handling of functions/tasks without top-level begin-end block, fixes #1231 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 18:06:14 +02:00
Clifford Wolf f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix 
Fix formatting for msys2 mingw build
 2019-08-02 16:37:57 +02:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Clifford Wolf 292f03355a Update JSON front-end to process new attr/param encoding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-01 12:48:22 +02:00
Clifford Wolf acd8bc0a74
Merge pull request #1233 from YosysHQ/clifford/defer 
Call "read_verilog" with -defer from "read"
 2019-07-31 13:30:52 +02:00
Clifford Wolf fc462c8243 Call "read_verilog" with -defer from "read" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:29:36 +02:00
David Shah 92694ea3a9 verilog_lexer: Increase YY_BUF_SIZE to 65536 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 13:35:39 +01:00
Jakob Wenzel e2fe8e0a4f initialize noblackbox and nowb in AstModule::clone 2019-07-22 10:37:40 +02:00
Miodrag Milanovic 6cce679b35 Fix typo, double "of" 2019-07-16 11:03:30 +02:00
William D. Jones da5d64d71e Fix missing semicolon in Windows-specific code in aigerparse.cc. 
Signed-off-by: William D. Jones <thor0505@comcast.net>
 2019-07-14 13:52:27 -04:00
whitequark b1f400aeb8 genrtlil: emit \src attribute on CaseRule. 2019-07-08 12:29:08 +00:00
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL. 
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
 2019-07-08 11:34:58 +00:00
Clifford Wolf e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-03 12:30:37 +02:00
Clifford Wolf ba36567908 Some cleanups in "ignore specify parser" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:22:10 +02:00
Clifford Wolf d206eca03b Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-02 11:36:26 +02:00
Eddie Hung b3f162e94e Replace log_assert() with meaningful log_error() 2019-06-28 12:54:44 -07:00
Clifford Wolf af74409749 Improve specify dummy parser, fixes #1144 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-28 10:21:16 +02:00
Eddie Hung 9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung 469f98b6bd Remove unneeded include 2019-06-27 11:20:40 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Clifford Wolf f6053b8810 Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:09:43 +02:00