Clifford Wolf
eb452ffb28
Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-23 10:32:54 +02:00
Clifford Wolf
9659f7a99e
Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc
2018-09-23 10:04:37 +02:00
Clifford Wolf
138ba71264
Update CHANGELOG
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-23 09:25:40 +02:00
Miodrag Milanovic
41affeeeb9
added prefix to FDirection constants, fixing windows build
2018-09-21 20:43:49 +02:00
Clifford Wolf
2867bf46a9
Update CHANGLELOG
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-21 16:27:07 +02:00
Clifford Wolf
bf189122a8
Update Changelog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-21 13:55:20 +02:00
Clifford Wolf
dc77ed1e88
Merge pull request #633 from mmicko/master
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Fix Cygwin build and document needed packages
2018-09-19 15:08:31 +02:00
Clifford Wolf
f1972b6c90
Merge pull request #631 from acw1251/master
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Fixed typo in "verilog_write" help message
2018-09-19 15:07:28 +02:00
Miodrag Milanovic
c5e9034834
Fix Cygwin build and document needed packages
2018-09-19 10:16:53 +02:00
acw1251
efac8a45a6
Fixed typo in "verilog_write" help message
2018-09-18 13:34:30 -04:00
Udi Finkelstein
c693f595c5
Merge branch 'master' into pr_reg_wire_error
2018-09-18 01:27:01 +03:00
Udi Finkelstein
f6fe73b31f
Fixed remaining cases where we check fo wire reg/wire incorrect assignments
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on Yosys-generated assignments.
In this case, offending code was:
module top(input in, output out);
function func;
input arg;
func = arg;
endfunction
assign out = func(in);
endmodule
2018-09-18 01:23:40 +03:00
Clifford Wolf
592a82c0ad
Merge pull request #625 from aman-goel/master
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Minor revision to -expose in setundef pass
2018-09-14 12:36:13 +02:00
Clifford Wolf
1936d4408e
Merge pull request #627 from acw1251/master
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Fixed minor typo in "sim" help message
2018-09-14 12:34:51 +02:00
acw1251
5fe16c25b8
Fixed minor typo in "sim" help message
2018-09-12 18:34:27 -04:00
Aman Goel
75c1f8d241
Minor revision to -expose in setundef pass
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Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
2018-09-10 21:44:36 -04:00
Clifford Wolf
51f1bbeeb0
Add iCE40 SB_SPRAM256KA simulation model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-10 11:57:24 +02:00
Clifford Wolf
12440fcc8f
Add $lut support to Verilog back-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-06 00:18:01 +02:00
Clifford Wolf
5d9d22f66d
Add "verific -L <int>" option
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-04 20:06:10 +02:00
Clifford Wolf
0b7a18470b
Add "make ystests"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-30 12:26:26 +02:00
Miodrag Milanović
d36d11936f
Add GCC to osx deps ( #620 )
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* Add GCC to osx deps
* Force gcc-7 install
2018-08-28 17:17:33 +02:00
Clifford Wolf
cf2ea21899
Merge pull request #619 from mmicko/master
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Remove mercurial, since it is not needed anymore
2018-08-28 13:37:11 +02:00
Miodrag Milanovic
92896a58be
Remove mercurial, since it is not needed anymore
2018-08-28 13:11:41 +02:00
Clifford Wolf
373244c5ab
Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes
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Add support for modules.
2018-08-28 12:04:49 +02:00
Jim Lawson
e217c6c52f
Merge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 12:13:04 -07:00
Jim Lawson
380c6f0e97
Remove unused functions.
2018-08-27 10:18:33 -07:00
Jim Lawson
604b5d4e20
Merge pull request #3 from YosysHQ/master
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merge with YosysHQ
2018-08-27 10:09:39 -07:00
Clifford Wolf
ddc1761f1a
Add "make coverage"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-27 14:22:21 +02:00
Clifford Wolf
9e845bd254
Add ENABLE_GCOV build option
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-27 13:27:05 +02:00
Clifford Wolf
96d79878b9
Merge pull request #617 from mmicko/master
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static link flag on main executable
2018-08-25 16:40:55 +02:00
Miodrag Milanovic
306a010e19
static link flag on main executable
2018-08-25 16:20:44 +02:00
Jim Lawson
93d19dc2fb
Add support for module instances.
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Don't pad logical operands to one bit.
Use operand width and signedness in $reduce_bool.
Shift amounts are unsigned and shouldn't be padded.
Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
2018-08-23 14:35:11 -07:00
Clifford Wolf
4d269f9b25
Merge pull request #610 from udif/udif_specify_round2
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More specify/endspecify fixes
2018-08-23 14:43:25 +02:00
Clifford Wolf
92c2a04e19
Merge pull request #614 from udif/pr_disable_dump_ptr
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Added -no_dump_ptr flag for AST dump options in 'read_verilog'
2018-08-23 14:41:41 +02:00
Udi Finkelstein
042b3074f8
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
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This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
2018-08-23 15:26:02 +03:00
Jim Lawson
2c0601eb6f
Merge pull request #1 from YosysHQ/master
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merge with YosysHQ master
2018-08-22 08:42:34 -07:00
Clifford Wolf
408077769f
Add "verific -work" help message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-22 17:22:24 +02:00
Clifford Wolf
4b02ee9162
Add Verific -work parameter
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-22 13:30:22 +02:00
Udi Finkelstein
fbfc677df3
Fixed all known specify/endspecify issues, without breaking 'make test'.
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Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
2018-08-20 17:27:45 +03:00
Udi Finkelstein
95241c8f4d
Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v ,
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(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
2018-08-20 00:08:08 +03:00
Clifford Wolf
05466790a6
Merge pull request #606 from cr1901/show-win
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`show` pass `-format` and `-viewer` improvements on Windows
2018-08-19 15:25:46 +02:00
Clifford Wolf
519fe50b94
Merge pull request #608 from mmicko/master
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Static builds and cross-compilation support
2018-08-18 19:17:42 +02:00
Miodrag Milanovic
75d1852943
no -fPIC for any static build
2018-08-18 19:17:02 +02:00
Miodrag Milanovic
443865ab87
respect DISABLE_ABC_THREADS if used
2018-08-18 18:21:28 +02:00
Miodrag Milanovic
45740236b6
Enable propagating ARCHFLAGS
2018-08-18 15:11:58 +02:00
Miodrag Milanovic
539053ab68
Added option to disable -fPIC on unsupported platforms
2018-08-18 14:14:17 +02:00
Miodrag Milanovic
3e20788c24
Added gcc-static for easier cross compilation
2018-08-18 14:00:55 +02:00
Clifford Wolf
620ebd3c6d
Merge pull request #575 from aman-goel/master
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Adds -expose option to setundef pass
2018-08-18 13:22:39 +02:00
Aman Goel
83b41260f6
Revision to expose option in setundef pass
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Corrects indentation
Simplifications and corrections
2018-08-18 09:08:07 +05:30
Aman Goel
61f002c908
Merge pull request #3 from YosysHQ/master
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Updates from official repo
2018-08-18 08:18:40 +05:30