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14052 Commits

Author SHA1 Message Date
David Shah c3eb346e1e
Merge pull request #2467 from YosysHQ/dave/nexus-carry-fix 
nexus: More efficient CO mapping
 2020-12-02 22:07:25 +00:00
whitequark 7067f0d788 cxxrtl: fix crashes caused by a floating or constant clock input. 
E.g. in:

    module test;
        wire clk = 0;
        reg data;
        always @(posedge clk)
            data <= 0;
    endmodule
 2020-12-02 21:43:25 +00:00
whitequark 2945e27020
Merge pull request #2446 from RobertBaruch/rtlil_format 
Adds appendix on RTLIL text format
 2020-12-02 19:50:51 +00:00
whitequark aa0a15a42c cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert. 
RTL contract violations and C++ contract violations are different:
the former depend on the netlist and will never violate memory safety
whereas the latter may. When loading a CXXRTL simulation into another
process, RTL contract violations should generally not crash it, while
C++ contract violations should.
 2020-12-02 19:41:00 +00:00
David Shah 264e924abb nexus: More efficient CO mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 17:08:39 +00:00
Miodrag Milanovic 1c4a18f66f Bump required Verific version 2020-12-02 15:18:04 +01:00
whitequark 5beab5bc17 cxxrtl: provide a way to perform unobtrusive power-on reset. 
Although it is always possible to destroy and recreate the design to
simulate a power-on reset, this has two drawbacks:
  * Black boxes are also destroyed and recreated, which causes them
    to reacquire their resources, which might be costly and/or erase
    important state.
  * Pointers into the design are invalidated and have to be acquired
    again, which is costly and might be very inconvenient if they are
    captured elsewhere (especially through the C API).
 2020-12-02 08:25:27 +00:00
Yosys Bot d021f4b400 Bump version 2020-12-02 00:10:06 +00:00
Claire Xen 7b0cfd5c36
Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines 
Fix SYNTHESIS always being defined in Verilog frontend
 2020-12-01 12:31:34 +01:00
Miodrag Milanović ef5b2777c3
Merge pull request #2460 from pepijndevos/simple-gowin 
add -noalu and -json option for apicula
 2020-12-01 09:18:37 +01:00
georgerennie c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
Pepijn de Vos f155826a70 add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
Julius Roob 2e23dfd96b Return correct modname when found in cache. 2020-11-26 13:31:22 +01:00
Gabriel Somlo 6a328e7032 fixup over commit 829b5cca to re-enable ABCEXTERNAL support 2020-11-26 06:12:12 -05:00
Gabriel Somlo 150b729b6f Add #include needed to build with gcc-11 
Suggested by Jeff Law <law@redhat.com>
 2020-11-26 06:12:12 -05:00
Yosys Bot 2116c58581 Bump version 2020-11-26 00:10:09 +00:00
whitequark 45725d3bdf
Merge pull request #2452 from whitequark/rtlil-remove-dot-identifiers 
rtlil: remove dotted identifiers
 2020-11-25 21:22:14 +00:00
Robert Baruch 2bb3fc654a Further juggles the wording of "character". 2020-11-25 12:02:35 -08:00
Robert Baruch 5d1bb79895 Clarifies how character encodings work. 2020-11-25 11:57:17 -08:00
Miodrag Milanović 180a8e5a45
Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments 
Generate only simple assignments in verilog backend
 2020-11-25 19:15:11 +01:00
Robert Baruch 1faf0e6dcc Clarifies whitespace and eol. 2020-11-25 10:06:22 -08:00
Robert Baruch 5615c41907 Cleans up doublequotes 2020-11-25 09:58:36 -08:00
Robert Baruch 09f6e9d6b6 Clarifies use of integers, and character set. 2020-11-25 09:53:39 -08:00
Miodrag Milanovic 7b093dca10 Add verilog backend option for simple_lhs 2020-11-25 18:21:41 +01:00
Robert Baruch 39af3e629f Clarifies processes, corrects some attributes 2020-11-25 08:59:25 -08:00
whitequark 015b476e56 rtlil: remove dotted identifiers. 
No one knows where they came from and they never did anything useful.
 2020-11-25 16:47:20 +00:00
Miodrag Milanovic addc493e8d generate only simple assignments in verilog backend 2020-11-25 17:43:28 +01:00
Claire Xen cf67e6a397
Merge pull request #2133 from dh73/nodev_head 
Adding latch tests for shift&mask AST dynamic part-select enhancements
 2020-11-25 09:44:23 +01:00
Robert Baruch be938b3094 Refactors for attributes. 2020-11-24 21:59:53 -08:00
whitequark c6b5b18a30
Merge pull request #2442 from cr1901/sccache 
Makefile: Add disabled-by-default ENABLE_SCCACHE config option.
 2020-11-25 02:48:39 +00:00
whitequark 2a39c785a2
Merge pull request #2450 from nitz/sim-vcd-filename 
Add rewrite_filename for sim -vcd argument.
 2020-11-25 02:48:10 +00:00
William D. Jones 9431033921 Makefile: Update ABCREV to bring in sccache fixes. 2020-11-24 21:32:27 -05:00
Yosys Bot 88c47a380b Bump version 2020-11-25 00:10:05 +00:00
Robert Baruch 278b542273 Cleans up some descriptions and syntax 
Now all rules ending in "-stmt" end in eol.
 2020-11-24 15:27:30 -08:00
Chris Dailey cdc802e4b7
Add rewrite_filename for sim -vcd argument. 2020-11-24 15:17:16 -05:00
whitequark bc085761e6
Merge pull request #2428 from whitequark/check-processes 
check: add support for processes
 2020-11-24 15:04:42 +00:00
Miodrag Milanović 5cf738b66a
Merge pull request #2448 from nitz/tcl-script-documentation-fixes 
Tcl script documentation fixes
 2020-11-24 07:51:56 +01:00
Miodrag Milanović b8d3f13307
Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parameters 
Add firrtl backend support for generic parameters in blackbox components
 2020-11-24 07:50:17 +01:00
nitz cc0d7244b8
tcl -h message only if YOSYS_ENABLE_TCL defined. 2020-11-23 21:48:44 -05:00
Sahand Kashani 930a6ae7db Formatting fixes 2020-11-23 10:55:09 +01:00
Robert Baruch d3d28e287f Adds missing "end" and eol to module. 2020-11-22 21:08:58 -08:00
Robert Baruch c5a2ae01cd Update to Values #2 2020-11-22 18:50:41 -08:00
Robert Baruch 5159dda826 Update to Values section 2020-11-22 18:48:21 -08:00
Robert Baruch 1034422c58 Adds appendix on RTLIL text format 2020-11-22 12:56:29 -08:00
Yosys Bot 949eb95593 Bump version 2020-11-21 00:10:06 +00:00
Miodrag Milanović de58e774ef
Merge pull request #2443 from YosysHQ/dave/nexus-mult-infer 
nexus: Multiplier inference support
 2020-11-20 10:30:56 +01:00
David Shah 9f241c9a42 nexus: DSP inference support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-20 08:45:55 +00:00
William D. Jones 296a23f489 Makefile: Add disabled-by-default ENABLE_SCCACHE config option. 2020-11-19 13:23:54 -05:00
Yosys Bot 5b35d953f7 Bump version 2020-11-19 00:10:10 +00:00
Miodrag Milanović c8d809897f
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim 
nexus: Add DSP simulation model
 2020-11-18 12:22:05 +01:00