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2401 Commits

Author SHA1 Message Date
Krystine Sherwin 27b8b4e81e
Docs: Fix missing groups 
$lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.
 2024-10-15 11:08:30 +13:00
Krystine Sherwin 1513366f21
Docs: Adding mux cell descriptions 
Also making ver2 cell descriptions consistently spaced.
 2024-10-15 07:37:34 +13:00
Krystine Sherwin dfe803b5c6
Docs: Comments from @jix 
- Unswap shift/shiftx
- Add brief overview to cell lib
- Clarify $div cell B input
- Clarify unary operators
- What is $modfloor
 2024-10-15 07:37:20 +13:00
Krystine Sherwin 4d84d7e69f
simlib.v: Add x-output tag 
Also a few extra cell help texts.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin ed92374263
simlib.v: Update case equality operators to v2 
Also tag as x-aware cells and add titles.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin b1025dbaa6
cellhelp.py: Cells can have tags 
Tags are added to the list of properties when exporting to `cells.json`.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin f70a66f5b3
Docs: Assert cell has group 
Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.
 2024-10-15 07:35:40 +13:00
Krystine Sherwin 5c4f7b4deb
Docs: $eqx aka case equality 2024-10-15 07:35:40 +13:00
Krystine Sherwin 596d914ead
simcells: Apply group tags 2024-10-15 07:35:40 +13:00
Krystine Sherwin 78b9dbd4ea
Docs: Assign remaining word cells to groups 
Move todos to correct place.
Add todo for x-prop cells.
 2024-10-15 07:35:40 +13:00
Krystine Sherwin 1374fc2e2b
cellref: Deprecate cell_library.rst 
Most of the word/coarse level cells have an assigned group and individual page.
The gate/fine level cells are all on one page.
Fix links to `cell_library.rst`.
 2024-10-15 07:34:52 +13:00
Krystine Sherwin 04b0ae540d
cellref: Move default help message to register.cc 
Drop the default help message from rst while still displaying it on the command line.
Fix command line formatting for older style help messages.
 2024-10-15 07:31:47 +13:00
Krystine Sherwin c662529316
Docs: Move binary operators to cell appendix 
Add binary group tag to relevant cells.
Remove content from `cell_library.rst` that is already moved.
 2024-10-15 07:31:47 +13:00
Krystine Sherwin 7c5b10fe50
cellref: Add json dump 
New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).
 2024-10-15 07:25:27 +13:00
Krystine Sherwin 06e5e18371
simlib.v: Autolink referenced cells in alu 2024-10-15 07:23:45 +13:00
Krystine Sherwin 21747c468c
Docs: Improve cell_help usage 
- Drop `cell_code` and instead map code lookups to the `cell_help` dict.
- Add helper functions to struct for checking and getting the right cell.
- Add `CellType` for cell to `write_cell_rst` function declaration in
  preparation for use in future.
- Iterate over `yosys_celltypes.cell_types` when exporting cell rst files,
  reporting errors for any cells defined in `cell_types` but not
  `cell_help_messages`.
 2024-10-15 07:23:45 +13:00
Krystine Sherwin 57cd8d29db
cellhelp: Add default format parse for simcells 
Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst.
Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
 2024-10-15 07:16:40 +13:00
Krystine Sherwin a2b2904ed8
cellhelp: Add source line to help 
Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
 2024-10-15 07:16:40 +13:00
Krystine Sherwin 784292626e
cellhelp: Rename short_desc to title 2024-10-15 07:16:39 +13:00
Krystine Sherwin 4662476ec8
Docs: Test $alu with v2 help format 2024-10-15 07:16:39 +13:00
Krystine Sherwin 600149a824
Docs: Add back message for empty help 2024-10-15 07:16:39 +13:00
Krystine Sherwin 6bbe763845
Docs: Put cell library help strings into a struct 
Allows for more expressive code when constructing help messages for cells.
Will also move extra logic in parsing help strings into the initial python parse instead of doing it in the C++ at export time.
 2024-10-15 07:16:39 +13:00
Emil J 1113b88cb2
Merge pull request #4649 from YosysHQ/emil/synth-xilinx-json 
synth_xilinx: add -json
 2024-10-14 06:45:14 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Emil J. Tywoniak 981b267d97 synth_xilinx: add -json 2024-10-09 19:24:32 +02:00
Martin Povišer 9018d06a33 quicklogic: Avoid carry chains in division mapping 
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
 2024-09-19 12:18:47 +02:00
Martin Povišer eeffca9470 simlib: Add `$buf` disclaimer 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 4d469f461b Add coarse-grain $buf buffer cell type 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
YRabbit ab35dff702 Gowin. Add the EMCU primitive. 
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:51 +10:00
Miodrag Milanović 598d010349
Merge pull request #4504 from YosysHQ/nanoxplore 
NanoXplore synthesis
 2024-09-03 10:19:44 +02:00
Miodrag Milanovic 556c705a89 Cleanup of synth_nanoxplore pass 2024-09-03 10:15:50 +02:00
Emil J d901b28d2c
Merge pull request #4546 from NachtSpyder04/main 
[Docs]:Add new cell type help messages
 2024-08-19 15:50:41 +02:00
David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files 
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
 2024-08-18 19:38:31 +01:00
NachtSpyder04 aa60255e0e update help messages that went beyond line length limit 2024-08-18 20:27:35 +05:30
Saish Karole 34aabd56cc
Apply suggestions from code review 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-08-18 20:12:53 +05:30
Saish Karole d80d4dc51c
[Docs]:Add new cell type help messages (#1) 
* add shift operators description

* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
 2024-08-17 15:47:00 +05:30
Miodrag Milanovic 54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 14e43139cb Run opt_merge, helps with inverted reset/load signals 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 220ddeac4d Set -mince and -minsrst 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7bf623a0c7 Fix simulation model warnings 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 262ad03cd3 Add iopads by default add option to disable and keep old one for compatibility 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f806c0d12 Added DDFR support 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 6876a27547 Add NX_DFR simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic eb30be6189 Impulse does not support these types but NG-ULTRA architecture does 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7601dc740b Some memory types are only supported on NG-LARGE 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4372487a6f raw must be 16 bits for nx tools to work 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f8ae93c0ea run setundef for all x inputs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00