Commit Graph

12894 Commits

Author SHA1 Message Date
Catherine 0486f61a35 write_verilog: emit zero width parameters as `.PARAM()`. 2024-01-11 13:13:04 +01:00
Dag Lem 3ed9030eb4 Optionally suppress output from display system tasks in read_verilog 2024-01-11 13:12:53 +01:00
Jannis Harder 510d137996 fmt: Allow non-constant $display calls in initial blocks
These are useful for formal verification with SBY where they can be used
to display solver chosen `rand const reg` signals and signals derived
from those.

The previous error message for non-constant initial $display statements
is downgraded to a log message. Constant initial $display statements
will be shown both during elaboration and become part of the RTLIL so
that the `sim` output is complete.
2024-01-11 13:01:28 +01:00
Jannis Harder 57b4e16acd sim: Include $display output in JSON summary
This allows tools like SBY to capture the $display output independent
from anything else sim might log. Additionally it provides source and
hierarchy locations for everything printed.
2024-01-11 12:01:39 +01:00
Martin Povišer eeadbb583e
Merge pull request #4069 from daglem/simplify-array-slice-assignment
Simplify and correct array slice assignment
2024-01-11 11:41:34 +01:00
github-actions[bot] f26495e54d Bump version 2024-01-11 00:16:28 +00:00
Dag Lem e0566eafdb Add test for rhs sign extension in array slice assignment 2024-01-10 21:15:00 +01:00
Dag Lem 23cd23efc5 Simplify and correct AST for array slice assignment
Corrects sign extension of the right hand side, and hopefully
makes the code simpler to understand.

Fixes #4064
2024-01-10 21:15:00 +01:00
Martin Povišer a921f5968e
Merge pull request #3875 from daglem/nowrshmsk-optimization
Optimization of nowrshmsk
2024-01-10 21:08:17 +01:00
Dag Lem 1a2b4759e8 Assign from rvalue via temporary register in nowrshmsk CASE
Avoid repeating complex rvalue expressions for each condition.
2024-01-10 20:40:01 +01:00
Dag Lem dbec704b49 Include x bits in test of lhs dynamic part-select 2024-01-10 20:28:36 +01:00
Dag Lem a105d2c050 Add torture test for (* nowrshmsk *) stride optimization 2024-01-10 20:28:36 +01:00
Dag Lem 2cab4ff173 Correction and optimization of nowrshmsk
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that
nowrshmsk is actually tested.

Stride is extracted from indexing of two-dimensional packed arrays and
variable slices on the form dst[i*stride +: width] = src, and is used
to optimize the generated CASE block.

Also uses less confusing variable names for indexing of lhs wires.
2024-01-10 20:28:36 +01:00
github-actions[bot] e131a7895a Bump version 2024-01-10 00:16:19 +00:00
Catherine bc9206f0f5 write_verilog: emit `casez` as `if/elif/else` whenever possible. 2024-01-09 14:49:20 +00:00
Miodrag Milanović 9e3d132050
Merge pull request #4121 from YosysHQ/macos_upgrade
Update macOS to Ventura
2024-01-09 15:05:15 +01:00
Catherine f6e36f0e54 cxxrtl: implement a generic record/replay interface.
This commit adds a reader/writer implementation for a file format
optimized for fast, single-pass storage and retrieval of design state
changes, as well as a recorder/replayer that integrate with the eval
and commit simulation steps to create replay logs and reproduce them
later.

This feature makes it possible to run a simulation once, recording
the stimulus as well as changes to the registers, and navigate to
a past time point in the simulation later without rerunning it.
Both the changes in inputs (stimulus) and changes in state are saved
so that navigation does not require calling `eval()` or `commit()`;
only a series of memory copy operations.

On a representative example of a SoC netlist, saving the replay log
while simulating it takes 150% of the time it would take to simulate
the same design without logging, which is a much lower overhead than
writing an equivalent full view (including memories) VCD waveform dump.
The replay log is also several times smaller than the VCD dump, and
more space savings are available as low hanging fruit.

Replaying the log has not been optimized and currently takes about
the same time as running the simulation in first place. However, it
is still useful since it provides fast navigation to an arbitrary time
point, something that rerunning the simulation does not allow for.

The current file format should be considered preliminary. It is not
very space-efficient, and my testing shows that a lot of time is spent
in the write() syscall in the kernel. Most likely, compression and/or
writing in another thread could improve performance by 10-20%. This
may be done at a later time.
2024-01-09 13:48:36 +00:00
Catherine a59d477098 cxxrtl: improve robustness of `cxxrtl::time`.
Avoid overflow during conversion for any representable raw value.
2024-01-09 13:44:39 +00:00
Catherine 5aaf1f1d39 cxxrtl: implement `value.get()` and `value.set()` for signed types. 2024-01-09 13:44:39 +00:00
Miodrag Milanovic c045c9a5c9 Update macOS to Ventura 2024-01-09 10:58:31 +01:00
github-actions[bot] 22370ad21e Bump version 2024-01-09 00:16:54 +00:00
N. Engelhardt 5a4db62870
Merge pull request #4111 from povik/verilog-back-nonpruned-case
write_verilog: Handle edge case with non-pruned processes
2024-01-08 16:38:56 +01:00
Martin Povišer 82fca50309 write_verilog: Handle edge case with non-pruned processes
This change only matters for processes that weren't processed by
`proc_rmdead` for which follow-up cases after a default case are treated
differently in Verilog and RTLIL semantics.
2024-01-06 17:05:02 +01:00
Martin Povišer 1ddb0892c1
Merge pull request #4101 from YosysHQ/micko/fix_init_order
Fix Windows build by forcing initialization order, fixes #4068
2024-01-06 10:46:34 +01:00
github-actions[bot] 30b795601c Bump version 2024-01-06 00:16:22 +00:00
Catherine f9dc1a2184 cxxrtl: fix comment wording. NFC 2024-01-05 20:41:16 +00:00
Catherine 3e358d9bfa cxxrtl: add a way to observe state changes during the commit step.
The commit observer is a structure containing a callback that is invoked
whenever the `commit()` method changes a wire or a memory. This allows
code external to the compiled netlist to react to changes in the design
state in a very efficient way. One example of how this feature can be
used is an efficient implementation of record/replay.

Note that the VCD writer does not benefit from this feature because it
must be able to react to changes in any debug items and not just those
that contain design state.
2024-01-05 19:02:00 +00:00
Catherine a94fafa8fe cxxrtl: add a representation of simulation timestamps.
While the VCD format separates the timescale and the timestep (likely
to allow representing the timestep with a small integer type), time in
CXXRTL is represented using a uniform 96-bit number, which allows for
a ±100 year range at femtosecond resolution.

The implementation uses `value<96>`, which provides fast arithmetic and
comparison operations, as well as conversion to/from a more common
representation of integer seconds plus femtoseconds.
2024-01-05 19:01:45 +00:00
Martin Povišer c72dc15f02
Merge pull request #4104 from daglem/struct-hierarchical-path
Correct hierarchical path names for structs and unions
2024-01-05 10:38:36 +01:00
Dag Lem 1bbea13f80 Correct hierarchical path names for structs and unions 2024-01-04 17:22:07 +01:00
Miodrag Milanovic 627fbc3477 Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
github-actions[bot] df65634e07 Bump version 2023-12-30 00:15:15 +00:00
Claire Xen 04fdb456f2
Merge pull request #4097 from YosysHQ/claire/constexpr
Add constexpr hashlib default constructors
2023-12-29 21:31:54 +01:00
Claire Xenia Wolf fb72dc1a40 Add constexpr hashlib default constructors
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-12-29 19:20:44 +01:00
github-actions[bot] ea7818d31b Bump version 2023-12-22 00:15:54 +00:00
Miodrag Milanović 86b8a1c5ae
Merge pull request #4087 from povik/lattice-dp8kc-fix
lattice: Fix mapping onto DP8KC for data width 1 or 2
2023-12-21 11:46:11 +01:00
Martin Povišer c028f25158 lattice: Disable broken port configuration in bram inference 2023-12-21 10:47:40 +01:00
Martin Povišer fc5c5172f8 lattice: Fix mapping onto DP8KC for data width 1 or 2 2023-12-20 23:42:12 +01:00
Miodrag Milanović a4ad7cb81a
Merge pull request #4049 from pepijndevos/patch-3
Enable bram for Gowin
2023-12-19 08:16:54 +01:00
N. Engelhardt d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash
tests: use /usr/bin/env for bash.
2023-12-18 16:33:35 +01:00
N. Engelhardt 78541be4d8
Merge pull request #3971 from povik/equiv_simple-fixes
Fixes to `equiv_simple`
2023-12-18 16:31:02 +01:00
N. Engelhardt 2615209dc1
Merge pull request #4078 from jix/smtbmc-cexenum-support
Improvements to smtbmc/witness to support counter-example enumeration
2023-12-18 16:20:52 +01:00
github-actions[bot] 70d35314db Bump version 2023-12-15 00:16:38 +00:00
Jannis Harder 94d7c22714 yosys-witness: Add aiw2yw --present-only to omit unused signals 2023-12-14 16:45:19 +01:00
Jannis Harder 3fab4d42ec smtbmc: Allow raw SMT-LIBv2 comamnds and expressions for --incremental 2023-12-14 16:44:21 +01:00
Jannis Harder 111085669b smtbmc: Use fewer smt commands while writing .yw traces
Depending on the used solver and design this can be a signficant
performance improvement.
2023-12-14 16:42:48 +01:00
Martin Povišer 449e3dbbd3 cxxrtl: Mask `bmux` result appropriately 2023-12-14 06:57:28 +00:00
github-actions[bot] 39fdde87a7 Bump version 2023-12-14 00:16:03 +00:00
Martin Povišer 112b11116d
Merge pull request #4072 from merryhime/cxxrtl-value-tests
cxxrtl: Add simple tests for cxxrtl::value from cxxrtl runtime
2023-12-13 18:11:26 +01:00
Merry 1dff3c83d9 tests/cxxrtl: Add -O2 2023-12-13 12:27:06 +00:00