mirror of https://github.com/YosysHQ/yosys.git
write_verilog: emit zero width parameters as `.PARAM()`.
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@ -1830,7 +1830,8 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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if (it != cell->parameters.begin())
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f << stringf(",");
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f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str());
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dump_const(f, it->second);
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if (it->second.size() > 0)
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dump_const(f, it->second);
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f << stringf(")");
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}
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f << stringf("\n%s" ")", indent.c_str());
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