Clifford Wolf
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45ee2ba3b8
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Fixed handling of [a-fxz?] in decimal constants
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2015-08-11 11:32:37 +02:00 |
Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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56c7d1e266
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Fixed two minor bugs in constant parsing
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2014-11-24 14:39:24 +01:00 |
Clifford Wolf
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87333f3ae2
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Added warning for use of 'z' constants in HDL
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2014-11-14 19:59:50 +01:00 |
Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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7f57bc8385
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Improved parsing of large integer constants
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2014-06-15 08:48:17 +02:00 |
Clifford Wolf
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0b47d907d3
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Fixed handling of unsized constants in verilog frontend
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2014-01-24 15:05:24 +01:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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46fbe9d262
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Added SAT generator and simple sat_solve command
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2013-06-07 13:59:13 +02:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |