Clifford Wolf
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a926a6afc2
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Remember global declarations and defines accross read_verilog calls
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2016-11-15 12:42:43 +01:00 |
Clifford Wolf
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fa535c0b00
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Some minor build fixes for Visual C
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2016-10-14 18:36:02 +02:00 |
Clifford Wolf
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bdc316db50
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Added $anyseq cell type
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2016-10-14 15:24:03 +02:00 |
Clifford Wolf
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53655d173b
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Added $global_clock verilog syntax support for creating $ff cells
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2016-10-14 12:33:56 +02:00 |
Clifford Wolf
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8ebba8a35f
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Added $ff and $_FF_ cell types
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2016-10-12 01:18:39 +02:00 |
Clifford Wolf
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59508c99b4
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define PATH_MAX if not defined by limits.h
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2016-10-11 12:12:09 +02:00 |
Clifford Wolf
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cb7dbf4070
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Improvements in assertpmux
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2016-09-07 12:42:16 +02:00 |
Clifford Wolf
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6f41e5277d
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Removed $aconst cell type
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2016-08-30 19:09:56 +02:00 |
Clifford Wolf
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eae390ae17
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Removed $predict again
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2016-08-28 21:35:33 +02:00 |
Clifford Wolf
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23afeadb5e
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Fixed handling of transparent bram rd ports on ROMs
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2016-08-27 17:06:22 +02:00 |
Clifford Wolf
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f8a77abfac
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Added glob support to all front-ends
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2016-08-22 15:05:57 +02:00 |
William D. Jones
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5299b17056
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Add MSYS2-compatible build.
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2016-08-16 14:41:59 -04:00 |
Clifford Wolf
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5767e4bc4d
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Use _Exit(0) on win32, always use _Exit(1) in log_error()
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2016-08-16 09:38:54 +02:00 |
Clifford Wolf
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39da8eddae
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Added log_const() API
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2016-08-09 19:56:10 +02:00 |
Yury Gribov
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f7730d43bb
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Use /proc/self/exe on Cygwin as well.
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2016-08-08 12:00:27 +02:00 |
Clifford Wolf
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8d88fcb270
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Added SatGen support for $anyconst
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2016-07-27 15:52:20 +02:00 |
Clifford Wolf
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9540be1d45
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Removed $predict support from SatGen
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2016-07-27 15:44:11 +02:00 |
Clifford Wolf
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4056312987
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Added $anyconst and $aconst
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2016-07-27 15:41:22 +02:00 |
Clifford Wolf
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a7b0769623
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Added "read_verilog -dump_rtlil"
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2016-07-27 15:40:17 +02:00 |
Clifford Wolf
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8537c4d206
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Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
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2016-07-25 16:39:25 +02:00 |
Clifford Wolf
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b1c432af56
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Improvements in CellEdgesDatabase
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2016-07-24 17:21:53 +02:00 |
Clifford Wolf
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f162b858f2
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Added CellEdgesDatabase API
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2016-07-24 13:59:57 +02:00 |
Clifford Wolf
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89deb412c6
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Added satgen initstate support
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2016-07-22 10:28:45 +02:00 |
Clifford Wolf
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5c166e76e5
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Added $initstate cell type and vlog function
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2016-07-21 14:23:22 +02:00 |
Clifford Wolf
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d7763634b6
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After reading the SV spec, using non-standard predict() instead of expect()
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2016-07-21 13:34:33 +02:00 |
Clifford Wolf
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721f1f5ecf
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Added basic support for $expect cells
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2016-07-13 16:56:17 +02:00 |
Ruben Undheim
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a8200a773f
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A few modifications after pull request comments
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
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2016-06-18 14:23:38 +02:00 |
Ruben Undheim
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178ff3e7f6
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Added support for SystemVerilog packages with localparam definitions
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2016-06-18 10:53:55 +02:00 |
Clifford Wolf
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ebece2b8d5
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Added $sop SAT model
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2016-06-17 17:47:30 +02:00 |
Clifford Wolf
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95757efb25
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Improved support for $sop cells
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2016-06-17 16:31:16 +02:00 |
Clifford Wolf
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52bb1b968d
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Added $sop cell type and "abc -sop"
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2016-06-17 13:50:09 +02:00 |
Clifford Wolf
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864eeadcd9
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Added missing "#define HASHLIB_H"
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2016-05-14 11:43:20 +02:00 |
Clifford Wolf
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570014800a
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Include <cmath> in yosys.h
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2016-05-08 10:50:39 +02:00 |
Clifford Wolf
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f103bfb9ba
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Fixes for MXE build
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2016-05-07 10:53:18 +02:00 |
Clifford Wolf
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9aa4b3309c
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Added "yosys -D ALL"
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2016-04-24 17:12:34 +02:00 |
Clifford Wolf
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0bc95f1e04
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Added "yosys -D" feature
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2016-04-21 23:28:37 +02:00 |
Clifford Wolf
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a07f893a5f
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Minor hashlib bugfix
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2016-04-16 23:20:11 +02:00 |
Clifford Wolf
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ace462237f
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Hashlib indenting fix
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2016-04-05 13:25:23 +02:00 |
Clifford Wolf
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2553319081
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Added ScriptPass helper class for script-like passes
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2016-03-31 11:16:34 +02:00 |
Clifford Wolf
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6f1b6dc322
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Added log_dump() support for dict<> and pool<> containers
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2016-03-31 09:57:44 +02:00 |
Clifford Wolf
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0db53284fd
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We have 2016 for a while now
|
2016-03-30 13:52:26 +02:00 |
Clifford Wolf
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48dbc75bed
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Added .vhd file extension support
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2016-03-30 13:24:49 +02:00 |
Clifford Wolf
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95784437ac
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Merge pull request #137 from ravenexp/master
Embed DATDIR make variable value into yosys binary.
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2016-03-28 16:54:23 +02:00 |
Sebastian Kuzminsky
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73870c1edf
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fix a cut-n-paste error in the -h help
|
2016-03-26 11:15:35 -06:00 |
Sergey Kvachonok
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963c0d2525
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Embed DATDIR make variable value into yosys binary.
Use it as the last resort in the share/ directory location search.
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2016-03-26 11:16:53 +03:00 |
Clifford Wolf
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45af4a4acf
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Use easyer-to-read unoptimized ceil_log2()
see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
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2016-02-15 23:06:18 +01:00 |
Clifford Wolf
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0c4b311242
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Fixed more visual studio warnings
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2016-02-14 09:35:25 +01:00 |
Clifford Wolf
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bcc873b805
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Fixed some visual studio warnings
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2016-02-13 17:31:24 +01:00 |
Clifford Wolf
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0d7fd2585e
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Added "int ceil_log2(int)" function
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2016-02-13 16:52:16 +01:00 |
Clifford Wolf
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ba407da187
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Added addBufGate module method
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2016-02-02 11:26:07 +01:00 |