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Merge branch 'xaig' into xc7mux

This commit is contained in:
Eddie Hung 2019-04-16 13:15:53 -07:00
parent fed1f0ba63 0c8a839f13
commit fc5fda595d
2 changed files with 1 additions and 3 deletions
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3
passes/techmap/abc9.cc
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@ -414,8 +414,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back(); RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module); sel.select(module);
// Adopt same behaviour as abc // Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
// TODO: How to specify don't-care to abc9?
Pass::call(design, "setundef -zero"); Pass::call(design, "setundef -zero");
Pass::call(design, "aigmap"); Pass::call(design, "aigmap");

1
tests/simple_abc9/run-test.sh
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@ -18,6 +18,5 @@ if ! which iverilog > /dev/null ; then
fi fi
cp ../simple/*.v . cp ../simple/*.v .
rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
DOLLAR='?' DOLLAR='?'
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'" exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"