diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f5f7add9a..b14eef485 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -414,8 +414,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	RTLIL::Selection& sel = design->selection_stack.back();
 	sel.select(module);
 
-	// Adopt same behaviour as abc
-	// TODO: How to specify don't-care to abc9?
+	// Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
 	Pass::call(design, "setundef -zero");
 
 	Pass::call(design, "aigmap");
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index bf48d007d..af003d52e 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -18,6 +18,5 @@ if ! which iverilog > /dev/null ; then
 fi
 
 cp ../simple/*.v .
-rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
 DOLLAR='?'
 exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"