yosys/backends/smt2/smtbmc.py

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#!/usr/bin/env python3
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#
# yosys -- Yosys Open SYnthesis Suite
#
# Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
#
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import os, sys, getopt, re
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##yosys-sys-path##
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from smtio import smtio, smtopts, mkvcd
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skip_steps = 0
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step_size = 1
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num_steps = 20
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vcdfile = None
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vlogtbfile = None
gentrace = False
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tempind = False
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assume_skipped = None
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topmod = None
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so = smtopts()
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def usage():
print("""
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yosys-smtbmc [options] <yosys_smt2_output>
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-t <num_steps>, -t <skip_steps>:<num_steps>
default: skip_steps=0, num_steps=20
-u <start_step>
assume asserts in skipped steps in BMC
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-S <step_size>
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prove <step_size> time steps at once
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-g
generate an arbitrary trace that satisfies
all assertions and assumptions.
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-i
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instead of BMC run temporal induction
-m <module_name>
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name of the top module
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--dump-vcd <vcd_filename>
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write trace to this VCD file
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(hint: use 'write_smt2 -wires' for maximum
coverage of signals in generated VCD file)
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""" + so.helpmsg())
sys.exit(1)
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try:
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opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:u:S:igm:", so.longopts + ["dump-vcd=", "dump-vlogtb="])
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except:
usage()
for o, a in opts:
if o == "-t":
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match = re.match(r"(\d+):(.*)", a)
if match:
skip_steps = int(match.group(1))
num_steps = int(match.group(2))
else:
num_steps = int(a)
elif o == "-u":
assume_skipped = int(a)
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elif o == "-S":
step_size = int(a)
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elif o == "--dump-vcd":
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vcdfile = a
elif o == "-i":
tempind = True
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elif o == "-g":
gentrace = True
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elif o == "-m":
topmod = a
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elif so.handle(o, a):
pass
else:
usage()
if len(args) != 1:
usage()
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smt = smtio(opts=so)
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print("%s Solver: %s" % (smt.timestamp(), so.solver))
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smt.setup("QF_AUFBV")
with open(args[0], "r") as f:
for line in f:
smt.write(line)
smt.info(line)
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if topmod is None:
topmod = smt.topmod
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assert topmod is not None
assert topmod in smt.modinfo
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def write_vcd_trace(steps):
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print("%s Writing model to VCD file." % smt.timestamp())
vcd = mkvcd(open(vcdfile, "w"))
for netpath in sorted(smt.hiernets(topmod)):
vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
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for i in range(steps):
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vcd.set_time(i)
path_list = sorted(smt.hiernets(topmod))
value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i)
for path, value in zip(path_list, value_list):
vcd.set_net([topmod] + path, value)
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vcd.set_time(steps)
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def print_failed_asserts(mod, state, path):
assert mod in smt.modinfo
if smt.get("(|%s_a| %s)" % (mod, state)) == "true":
return
for cellname, celltype in smt.modinfo[mod].cells.items():
print_failed_asserts(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + cellname)
for assertfun, assertinfo in smt.modinfo[mod].asserts.items():
if smt.get("(|%s| %s)" % (assertfun, state)) == "false":
print("%s Assert failed in %s: %s" % (smt.timestamp(), path, assertinfo))
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if tempind:
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retstatus = False
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skip_counter = step_size
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for step in range(num_steps, -1, -1):
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smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
smt.write("(assert (%s_u s%d))" % (topmod, step))
smt.write("(assert (%s_h s%d))" % (topmod, step))
smt.write("(assert (not (%s_is s%d)))" % (topmod, step))
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if step == num_steps:
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smt.write("(assert (not (%s_a s%d)))" % (topmod, step))
else:
smt.write("(assert (%s_t s%d s%d))" % (topmod, step, step+1))
smt.write("(assert (%s_a s%d))" % (topmod, step))
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if step > num_steps-skip_steps:
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print("%s Skipping induction in step %d.." % (smt.timestamp(), step))
continue
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skip_counter += 1
if skip_counter < step_size:
print("%s Skipping induction in step %d.." % (smt.timestamp(), step))
continue
skip_counter = 0
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print("%s Trying induction in step %d.." % (smt.timestamp(), step))
if smt.check_sat() == "sat":
if step == 0:
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print("%s Temporal induction failed!" % smt.timestamp())
print_failed_asserts(topmod, "s%d" % step, topmod)
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if vcdfile is not None:
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write_vcd_trace(num_steps+1)
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else:
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print("%s Temporal induction successful." % smt.timestamp())
retstatus = True
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break
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elif gentrace:
retstatus = True
for step in range(num_steps):
smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
smt.write("(assert (%s_u s%d))" % (topmod, step))
smt.write("(assert (%s_a s%d))" % (topmod, step))
smt.write("(assert (%s_h s%d))" % (topmod, step))
if step == 0:
smt.write("(assert (%s_i s0))" % (topmod))
smt.write("(assert (%s_is s0))" % (topmod))
else:
smt.write("(assert (%s_t s%d s%d))" % (topmod, step-1, step))
smt.write("(assert (not (%s_is s%d)))" % (topmod, step))
print("%s Creating trace of length %d.." % (smt.timestamp(), num_steps))
if smt.check_sat() == "sat":
if vcdfile is not None:
write_vcd_trace(num_steps)
else:
print("%s Creating trace failed!" % smt.timestamp())
retstatus = False
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else: # not tempind, not gentrace
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step = 0
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retstatus = True
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while step < num_steps:
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smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
smt.write("(assert (%s_u s%d))" % (topmod, step))
smt.write("(assert (%s_h s%d))" % (topmod, step))
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if step == 0:
smt.write("(assert (%s_i s0))" % (topmod))
smt.write("(assert (%s_is s0))" % (topmod))
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else:
smt.write("(assert (%s_t s%d s%d))" % (topmod, step-1, step))
smt.write("(assert (not (%s_is s%d)))" % (topmod, step))
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if step < skip_steps:
if assume_skipped is not None and step >= assume_skipped:
print("%s Skipping step %d (and assuming pass).." % (smt.timestamp(), step))
smt.write("(assert (%s_a s%d))" % (topmod, step))
else:
print("%s Skipping step %d.." % (smt.timestamp(), step))
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step += 1
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continue
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last_check_step = step
for i in range(1, step_size):
if step+i < num_steps:
smt.write("(declare-fun s%d () %s_s)" % (step+i, topmod))
smt.write("(assert (%s_u s%d))" % (topmod, step+i))
smt.write("(assert (%s_h s%d))" % (topmod, step+i))
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smt.write("(assert (%s_t s%d s%d))" % (topmod, step+i-1, step+i))
last_check_step = step+i
if last_check_step == step:
print("%s Checking asserts in step %d.." % (smt.timestamp(), step))
else:
print("%s Checking asserts in steps %d to %d.." % (smt.timestamp(), step, last_check_step))
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smt.write("(push 1)")
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smt.write("(assert (not (and %s)))" % " ".join(["(%s_a s%d)" % (topmod, i) for i in range(step, last_check_step+1)]))
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if smt.check_sat() == "sat":
print("%s BMC failed!" % smt.timestamp())
print_failed_asserts(topmod, "s%d" % step, topmod)
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if vcdfile is not None:
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write_vcd_trace(step+step_size)
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retstatus = False
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break
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else: # unsat
smt.write("(pop 1)")
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for i in range(step, last_check_step+1):
smt.write("(assert (%s_a s%d))" % (topmod, i))
step += step_size
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smt.write("(exit)")
smt.wait()
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print("%s Status: %s" % (smt.timestamp(), "PASSED" if retstatus else "FAILED (!)"))
sys.exit(0 if retstatus else 1)