mirror of https://github.com/YosysHQ/yosys.git
111 lines
2.5 KiB
Python
111 lines
2.5 KiB
Python
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#!/usr/bin/env python3
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import os, sys, getopt, re
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from smtio import smtio, smtopts, mkvcd
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steps = 20
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vcdfile = None
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tempind = False
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topmod = "main"
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so = smtopts()
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def usage():
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print("""
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python3 smtbmc.py [options] <yosys_smt2_output>
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-t <steps>
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default: 20
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-c <vcd_filename>
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write counter-example to this VCD file
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-i
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instead of BMC run temporal induction
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-m <module_name>
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name of the top module, default: main
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""" + so.helpmsg())
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sys.exit(1)
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try:
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opts, args = getopt.getopt(sys.argv[1:], so.optstr + "t:c:im:")
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except:
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usage()
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for o, a in opts:
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if o == "-t":
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steps = int(a)
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elif o == "-c":
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vcdfile = a
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elif o == "-i":
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tempind = True
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print("FIXME: temporal induction not yet implemented!")
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assert False
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elif so.handle(o, a):
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pass
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else:
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usage()
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if len(args) != 1:
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usage()
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smt = smtio(opts=so)
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print("Solver: %s" % so.solver)
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smt.setup("QF_AUFBV")
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debug_nets = set()
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debug_nets_re = re.compile(r"^; yosys-smt2-(input|output|register|wire) (\S+) (\d+)")
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with open(args[0], "r") as f:
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for line in f:
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match = debug_nets_re.match(line)
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if match:
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debug_nets.add(match.group(2))
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smt.write(line)
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def write_vcd_model():
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print("%s Writing model to VCD file." % smt.timestamp())
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vcd = mkvcd(open(vcdfile, "w"))
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for netname in sorted(debug_nets):
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width = len(smt.get_net_bin("main", netname, "s0"))
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vcd.add_net(netname, width)
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for i in range(step+1):
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vcd.set_time(i)
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for netname in debug_nets:
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vcd.set_net(netname, smt.get_net_bin("main", netname, "s%d" % i))
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vcd.set_time(step+1)
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for step in range(steps):
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smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
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smt.write("(assert (%s_u s0))" % (topmod))
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if step == 0:
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smt.write("(assert (%s_i s0))" % (topmod))
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else:
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smt.write("(assert (%s_t s%d s%d))" % (topmod, step-1, step))
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print("%s Checking sequence of length %d.." % (smt.timestamp(), step))
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smt.write("(push 1)")
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smt.write("(assert (not (%s_a s%d)))" % (topmod, step))
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if smt.check_sat() == "sat":
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print("%s BMC failed!" % smt.timestamp())
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if vcdfile is not None:
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write_vcd_model()
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break
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else: # unsat
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smt.write("(pop 1)")
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smt.write("(assert (%s_a s%d))" % (topmod, step))
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print("%s Done." % smt.timestamp())
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smt.write("(exit)")
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smt.wait()
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