yosys/tests/arch/anlogic/add_sub.ys

read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:AL_MAP_ADDER
select -assert-count 4 t:AL_MAP_LUT1

select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
Share common tests 2019-10-18 05:19:59 -05:00			`read_verilog ../common/add_sub.v`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`hierarchy -top top`
hierarchy - proc reorder 2019-10-18 02:06:43 -05:00			`proc`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check`
			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
			`cd top # Constrain all select calls below inside the top module`
			`select -assert-count 10 t:AL_MAP_ADDER`
			`select -assert-count 4 t:AL_MAP_LUT1`

Cleanup and formating 2019-10-04 04:09:59 -05:00			`select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D`