2013-01-05 04:13:26 -06:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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2013-02-27 02:32:19 -06:00
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#include "libs/sha1/sha1.h"
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2013-01-05 04:13:26 -06:00
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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2014-09-27 09:17:53 -05:00
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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2016-03-31 01:52:49 -05:00
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struct OptMergeWorker
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2013-01-05 04:13:26 -06:00
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap assign_map;
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2014-02-04 05:02:47 -06:00
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SigMap dff_init_map;
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2015-05-31 07:24:34 -05:00
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bool mode_share_all;
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2013-01-05 04:13:26 -06:00
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CellTypes ct;
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int total_count;
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2020-03-10 18:13:44 -05:00
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SHA1 checksum;
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2013-01-05 04:13:26 -06:00
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2016-03-31 02:58:55 -05:00
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static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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2020-04-02 11:51:32 -05:00
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SigSpec sig_s = conn.at(ID::S);
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2019-08-15 16:50:10 -05:00
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SigSpec sig_b = conn.at(ID::B);
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2016-03-31 02:58:55 -05:00
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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vector<pair<SigBit, SigSpec>> sb_pairs;
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for (int i = 0; i < s_width; i++)
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sb_pairs.push_back(pair<SigBit, SigSpec>(sig_s[i], sig_b.extract(i*width, width)));
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std::sort(sb_pairs.begin(), sb_pairs.end());
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2020-04-02 11:51:32 -05:00
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conn[ID::S] = SigSpec();
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2019-08-15 16:50:10 -05:00
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conn[ID::B] = SigSpec();
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2016-03-31 02:58:55 -05:00
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for (auto &it : sb_pairs) {
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2020-04-02 11:51:32 -05:00
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conn[ID::S].append(it.first);
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2019-08-15 16:50:10 -05:00
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conn[ID::B].append(it.second);
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2016-03-31 02:58:55 -05:00
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}
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}
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2013-01-05 04:13:26 -06:00
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std::string int_to_hash_string(unsigned int v)
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{
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if (v == 0)
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return "0";
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std::string str = "";
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while (v > 0) {
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str += 'a' + (v & 15);
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v = v >> 4;
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}
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return str;
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}
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std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
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{
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2020-03-10 18:13:44 -05:00
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vector<string> hash_conn_strings;
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2014-08-02 06:11:01 -05:00
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std::string hash_string = cell->type.str() + "\n";
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2013-01-05 04:13:26 -06:00
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2014-12-26 03:53:21 -06:00
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const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
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2013-03-29 05:01:26 -05:00
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2019-08-09 11:58:14 -05:00
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
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ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
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2013-03-29 05:01:26 -05:00
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alt_conn = *conn;
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2019-08-15 16:50:10 -05:00
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if (assign_map(alt_conn.at(ID::A)) < assign_map(alt_conn.at(ID::B))) {
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alt_conn[ID::A] = conn->at(ID::B);
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alt_conn[ID::B] = conn->at(ID::A);
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2013-03-29 05:01:26 -05:00
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}
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conn = &alt_conn;
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2013-03-29 05:19:21 -05:00
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} else
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2019-08-09 11:58:14 -05:00
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if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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2013-03-29 05:19:21 -05:00
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alt_conn = *conn;
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2019-08-15 16:50:10 -05:00
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assign_map.apply(alt_conn.at(ID::A));
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alt_conn.at(ID::A).sort();
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2013-03-29 05:19:21 -05:00
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conn = &alt_conn;
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} else
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2019-08-09 11:58:14 -05:00
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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2013-03-29 05:19:21 -05:00
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alt_conn = *conn;
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2019-08-15 16:50:10 -05:00
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assign_map.apply(alt_conn.at(ID::A));
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alt_conn.at(ID::A).sort_and_unify();
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2013-03-29 05:19:21 -05:00
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conn = &alt_conn;
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2016-03-31 02:58:55 -05:00
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} else
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2019-08-09 11:58:14 -05:00
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if (cell->type == ID($pmux)) {
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2016-03-31 02:58:55 -05:00
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alt_conn = *conn;
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2019-08-15 16:50:10 -05:00
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assign_map.apply(alt_conn.at(ID::A));
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assign_map.apply(alt_conn.at(ID::B));
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2020-04-02 11:51:32 -05:00
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assign_map.apply(alt_conn.at(ID::S));
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2016-03-31 02:58:55 -05:00
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sort_pmux_conn(alt_conn);
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conn = &alt_conn;
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2013-03-29 05:01:26 -05:00
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}
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for (auto &it : *conn) {
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2020-03-10 18:13:44 -05:00
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RTLIL::SigSpec sig;
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if (cell->output(it.first)) {
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2020-04-08 10:36:12 -05:00
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if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
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2020-03-10 18:13:44 -05:00
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// For the 'Q' output of state elements,
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// use its (* init *) attribute value
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for (const auto &b : dff_init_map(it.second))
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sig.append(b.wire ? State::Sx : b);
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}
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else
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continue;
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}
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else
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sig = assign_map(it.second);
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2016-03-31 02:58:55 -05:00
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string s = "C " + it.first.str() + "=";
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2014-07-22 13:15:14 -05:00
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for (auto &chunk : sig.chunks()) {
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2013-01-05 04:13:26 -06:00
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if (chunk.wire)
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2016-03-31 02:58:55 -05:00
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s += "{" + chunk.wire->name.str() + " " +
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2013-01-05 04:13:26 -06:00
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int_to_hash_string(chunk.offset) + " " +
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int_to_hash_string(chunk.width) + "}";
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else
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2016-03-31 02:58:55 -05:00
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s += RTLIL::Const(chunk.data).as_string();
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2013-01-05 04:13:26 -06:00
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}
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2016-03-31 02:58:55 -05:00
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hash_conn_strings.push_back(s + "\n");
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2013-01-05 04:13:26 -06:00
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}
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2020-03-10 18:13:44 -05:00
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for (auto &it : cell->parameters)
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hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
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2016-03-31 02:58:55 -05:00
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std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
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for (auto it : hash_conn_strings)
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hash_string += it;
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2020-03-10 18:13:44 -05:00
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checksum.update(hash_string);
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return checksum.final();
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2013-01-05 04:13:26 -06:00
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}
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2020-03-10 18:13:44 -05:00
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
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2013-01-05 04:13:26 -06:00
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{
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2020-03-10 18:13:44 -05:00
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log_assert(cell1 != cell2);
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if (cell1->type != cell2->type) return false;
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if (cell1->parameters != cell2->parameters)
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return false;
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if (cell1->connections_.size() != cell2->connections_.size())
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return false;
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for (const auto &it : cell1->connections_)
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if (!cell2->connections_.count(it.first))
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return false;
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decltype(Cell::connections_) conn1, conn2;
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conn1.reserve(cell1->connections_.size());
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conn2.reserve(cell1->connections_.size());
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for (const auto &it : cell1->connections_) {
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if (cell1->output(it.first)) {
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2020-04-02 11:51:32 -05:00
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if (it.first == ID::Q && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
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2020-03-10 18:13:44 -05:00
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cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
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2020-04-02 11:51:32 -05:00
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cell1->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
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2020-03-10 18:13:44 -05:00
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// For the 'Q' output of state elements,
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// use the (* init *) attribute value
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auto &sig1 = conn1[it.first];
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for (const auto &b : dff_init_map(it.second))
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sig1.append(b.wire ? State::Sx : b);
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auto &sig2 = conn2[it.first];
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for (const auto &b : dff_init_map(cell2->getPort(it.first)))
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sig2.append(b.wire ? State::Sx : b);
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}
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else {
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conn1[it.first] = RTLIL::SigSpec();
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conn2[it.first] = RTLIL::SigSpec();
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}
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}
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else {
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conn1[it.first] = assign_map(it.second);
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conn2[it.first] = assign_map(cell2->getPort(it.first));
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}
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2013-01-05 04:13:26 -06:00
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}
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2019-08-09 11:58:14 -05:00
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if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
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cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) {
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2019-08-15 16:50:10 -05:00
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if (conn1.at(ID::A) < conn1.at(ID::B)) {
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RTLIL::SigSpec tmp = conn1[ID::A];
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conn1[ID::A] = conn1[ID::B];
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conn1[ID::B] = tmp;
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2013-03-29 05:01:26 -05:00
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}
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2019-08-15 16:50:10 -05:00
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if (conn2.at(ID::A) < conn2.at(ID::B)) {
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RTLIL::SigSpec tmp = conn2[ID::A];
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conn2[ID::A] = conn2[ID::B];
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conn2[ID::B] = tmp;
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2013-03-29 05:01:26 -05:00
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}
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2013-03-29 05:19:21 -05:00
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} else
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2019-08-09 11:58:14 -05:00
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if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) {
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2019-08-15 16:50:10 -05:00
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conn1[ID::A].sort();
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conn2[ID::A].sort();
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2013-03-29 05:19:21 -05:00
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} else
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2019-08-09 11:58:14 -05:00
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if (cell1->type == ID($reduce_and) || cell1->type == ID($reduce_or) || cell1->type == ID($reduce_bool)) {
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2019-08-15 16:50:10 -05:00
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conn1[ID::A].sort_and_unify();
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conn2[ID::A].sort_and_unify();
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2016-03-31 02:58:55 -05:00
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} else
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2019-08-09 11:58:14 -05:00
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if (cell1->type == ID($pmux)) {
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2016-03-31 02:58:55 -05:00
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sort_pmux_conn(conn1);
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sort_pmux_conn(conn2);
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2013-03-29 05:01:26 -05:00
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}
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2020-03-10 18:13:44 -05:00
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return conn1 == conn2;
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2013-01-05 04:13:26 -06:00
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}
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2016-03-31 01:52:49 -05:00
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OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
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2015-05-31 07:24:34 -05:00
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design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
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2013-01-05 04:13:26 -06:00
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{
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total_count = 0;
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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if (mode_nomux) {
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2019-08-09 11:58:14 -05:00
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ct.cell_types.erase(ID($mux));
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ct.cell_types.erase(ID($pmux));
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2013-01-05 04:13:26 -06:00
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}
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2019-08-09 11:58:14 -05:00
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ct.cell_types.erase(ID($tribuf));
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ct.cell_types.erase(ID($_TBUF_));
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ct.cell_types.erase(ID($anyseq));
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ct.cell_types.erase(ID($anyconst));
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ct.cell_types.erase(ID($allseq));
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ct.cell_types.erase(ID($allconst));
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2017-02-28 15:17:00 -06:00
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2013-01-05 04:13:26 -06:00
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log("Finding identical cells in module `%s'.\n", module->name.c_str());
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assign_map.set(module);
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2014-02-04 05:02:47 -06:00
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dff_init_map.set(module);
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2014-07-26 18:49:51 -05:00
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for (auto &it : module->wires_)
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2020-04-02 11:51:32 -05:00
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if (it.second->attributes.count(ID::init) != 0) {
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Const initval = it.second->attributes.at(ID::init);
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2017-02-09 09:06:58 -06:00
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for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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dff_init_map.add(SigBit(it.second, i), initval[i]);
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}
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2014-02-04 05:02:47 -06:00
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2013-01-05 04:13:26 -06:00
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bool did_something = true;
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while (did_something)
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{
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std::vector<RTLIL::Cell*> cells;
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2014-07-26 18:51:45 -05:00
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cells.reserve(module->cells_.size());
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for (auto &it : module->cells_) {
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2015-05-31 07:24:34 -05:00
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if (!design->selected(module, it.second))
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continue;
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|
if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known()))
|
2013-01-05 04:13:26 -06:00
|
|
|
cells.push_back(it.second);
|
|
|
|
}
|
|
|
|
|
|
|
|
did_something = false;
|
2020-03-16 14:44:33 -05:00
|
|
|
dict<std::string, RTLIL::Cell*> sharemap;
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto cell : cells)
|
|
|
|
{
|
2020-03-10 18:13:44 -05:00
|
|
|
if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
auto hash = hash_cell_parameters_and_connections(cell);
|
|
|
|
auto r = sharemap.insert(std::make_pair(hash, cell));
|
|
|
|
if (!r.second) {
|
|
|
|
if (compare_cell_parameters_and_connections(cell, r.first->second)) {
|
|
|
|
if (cell->has_keep_attr()) {
|
|
|
|
if (r.first->second->has_keep_attr())
|
|
|
|
continue;
|
|
|
|
std::swap(r.first->second, cell);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
did_something = true;
|
|
|
|
log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str());
|
|
|
|
for (auto &it : cell->connections()) {
|
|
|
|
if (cell->output(it.first)) {
|
|
|
|
RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
|
|
|
|
log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
|
|
|
|
log_signal(it.second), log_signal(other_sig));
|
|
|
|
module->connect(RTLIL::SigSig(it.second, other_sig));
|
|
|
|
assign_map.add(it.second, other_sig);
|
|
|
|
|
2020-06-30 13:57:35 -05:00
|
|
|
if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
|
2020-03-10 18:13:44 -05:00
|
|
|
for (auto c : it.second.chunks()) {
|
2020-04-02 11:51:32 -05:00
|
|
|
auto jt = c.wire->attributes.find(ID::init);
|
2020-03-10 18:13:44 -05:00
|
|
|
if (jt == c.wire->attributes.end())
|
|
|
|
continue;
|
|
|
|
for (int i = c.offset; i < c.offset + c.width; i++)
|
|
|
|
jt->second[i] = State::Sx;
|
|
|
|
}
|
|
|
|
dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
|
2019-12-13 12:26:37 -06:00
|
|
|
}
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2020-03-10 18:13:44 -05:00
|
|
|
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
|
|
|
|
module->remove(cell);
|
|
|
|
total_count++;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-04-22 10:25:52 -05:00
|
|
|
|
|
|
|
log_suppressed();
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2016-03-31 01:52:49 -05:00
|
|
|
struct OptMergePass : public Pass {
|
|
|
|
OptMergePass() : Pass("opt_merge", "consolidate identical cells") { }
|
2020-06-18 18:34:52 -05:00
|
|
|
void help() override
|
2013-03-01 01:58:55 -06:00
|
|
|
{
|
|
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
|
|
log("\n");
|
2016-03-31 01:52:49 -05:00
|
|
|
log(" opt_merge [options] [selection]\n");
|
2013-03-01 01:58:55 -06:00
|
|
|
log("\n");
|
|
|
|
log("This pass identifies cells with identical type and input signals. Such cells\n");
|
|
|
|
log("are then merged to one cell.\n");
|
|
|
|
log("\n");
|
|
|
|
log(" -nomux\n");
|
|
|
|
log(" Do not merge MUX cells.\n");
|
|
|
|
log("\n");
|
2015-05-31 07:24:34 -05:00
|
|
|
log(" -share_all\n");
|
|
|
|
log(" Operate on all cell types, not just built-in types.\n");
|
|
|
|
log("\n");
|
2013-03-01 01:58:55 -06:00
|
|
|
}
|
2020-06-18 18:34:52 -05:00
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2016-04-21 16:28:37 -05:00
|
|
|
log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
bool mode_nomux = false;
|
2015-05-31 07:24:34 -05:00
|
|
|
bool mode_share_all = false;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
size_t argidx;
|
|
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
|
|
std::string arg = args[argidx];
|
|
|
|
if (arg == "-nomux") {
|
|
|
|
mode_nomux = true;
|
|
|
|
continue;
|
|
|
|
}
|
2015-05-31 07:24:34 -05:00
|
|
|
if (arg == "-share_all") {
|
|
|
|
mode_share_all = true;
|
|
|
|
continue;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
extra_args(args, argidx, design);
|
|
|
|
|
|
|
|
int total_count = 0;
|
2015-02-03 16:45:01 -06:00
|
|
|
for (auto module : design->selected_modules()) {
|
2016-03-31 01:52:49 -05:00
|
|
|
OptMergeWorker worker(design, module, mode_nomux, mode_share_all);
|
2013-01-05 04:13:26 -06:00
|
|
|
total_count += worker.total_count;
|
|
|
|
}
|
|
|
|
|
2014-08-30 12:37:12 -05:00
|
|
|
if (total_count)
|
|
|
|
design->scratchpad_set_bool("opt.did_something", true);
|
2013-01-05 04:13:26 -06:00
|
|
|
log("Removed a total of %d cells.\n", total_count);
|
|
|
|
}
|
2016-03-31 01:52:49 -05:00
|
|
|
} OptMergePass;
|
2015-07-02 04:14:30 -05:00
|
|
|
|
2014-09-27 09:17:53 -05:00
|
|
|
PRIVATE_NAMESPACE_END
|