2013-10-27 03:33:47 -05:00
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OBJS += techlibs/xilinx/synth_xilinx.o
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2019-12-18 06:42:26 -06:00
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OBJS += techlibs/xilinx/xilinx_dffopt.o
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2013-10-27 03:33:47 -05:00
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2015-04-06 10:07:10 -05:00
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GENFILES += techlibs/xilinx/brams_init_36.vh
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GENFILES += techlibs/xilinx/brams_init_32.vh
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GENFILES += techlibs/xilinx/brams_init_18.vh
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GENFILES += techlibs/xilinx/brams_init_16.vh
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2019-07-02 07:28:35 -05:00
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GENFILES += techlibs/xilinx/brams_init_9.vh
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GENFILES += techlibs/xilinx/brams_init_8.vh
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2015-04-06 10:07:10 -05:00
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EXTRA_OBJS += techlibs/xilinx/brams_init.mk
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.SECONDARY: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py
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2015-08-16 14:15:07 -05:00
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$(Q) mkdir -p techlibs/xilinx
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2019-10-19 01:04:52 -05:00
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$(P) $(PYTHON_EXECUTABLE) $<
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2015-08-12 08:04:44 -05:00
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$(Q) touch $@
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2015-04-06 10:07:10 -05:00
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techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_18.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk
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2019-07-02 07:28:35 -05:00
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techlibs/xilinx/brams_init_9.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
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2015-04-06 10:07:10 -05:00
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2015-01-18 12:43:54 -06:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
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2015-01-07 17:23:18 -06:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
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2020-02-04 08:35:47 -06:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sa_brams.txt))
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2020-02-03 11:50:33 -06:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_brams.txt))
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2019-07-02 07:28:35 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
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2019-10-18 07:24:19 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt))
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2019-07-02 07:28:35 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
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2019-10-18 07:24:19 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v))
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2019-10-18 08:02:57 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v))
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2020-02-03 11:37:28 -06:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut4_lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut6_lutrams.txt))
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2019-07-18 16:51:55 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
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2015-01-18 12:43:54 -06:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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2019-08-15 22:14:30 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
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2019-03-01 13:21:07 -06:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
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2019-06-14 14:50:24 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
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2019-10-08 12:00:30 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
|
2019-06-29 21:37:04 -05:00
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2019-10-04 13:04:10 -05:00
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
|
2015-01-04 07:23:30 -06:00
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|
2015-08-16 14:15:07 -05:00
|
|
|
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
|
|
|
|
|
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
|
|
|
|
|
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
|
|
|
|
|
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
|
2019-07-02 07:28:35 -05:00
|
|
|
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_9.vh))
|
|
|
|
|
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_8.vh))
|
2015-08-16 14:15:07 -05:00
|
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|
