yosys/techlibs/xilinx/xc7_xcu_brams.txt

# Virtex 6, Series 7, Ultrascale, Ultrascale Plus block RAM rules.

bram $__XILINX_RAMB36_SDP
  init 1
  abits 9
  dbits 72
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 8
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_SDP
  init 1
  abits 9
  dbits 36
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 4
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB36_TDP
  init 1
  abits 10     @a10d36
  dbits 36     @a10d36
  abits 11     @a11d18
  dbits 18     @a11d18
  abits 12     @a12d9
  dbits  9     @a12d9
  abits 13     @a13d4
  dbits  4     @a13d4
  abits 14     @a14d2
  dbits  2     @a14d2
  abits 15     @a15d1
  dbits  1     @a15d1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 4   @a10d36
  enable 1 2   @a11d18
  enable 1 1   @a12d9 @a13d4 @a14d2 @a15d1
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_TDP
  init 1
  abits 10     @a10d18
  dbits 18     @a10d18
  abits 11     @a11d9
  dbits  9     @a11d9
  abits 12     @a12d4
  dbits  4     @a12d4
  abits 13     @a13d2
  dbits  2     @a13d2
  abits 14     @a14d1
  dbits  1     @a14d1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 2   @a10d18
  enable 1 1   @a11d9 @a12d4 @a13d2 @a14d1
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

# The "min bits" value were taken from:
# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
# v1.14 ed., p 29-30, July, 2019.
# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

match $__XILINX_RAMB36_SDP
  attribute !ram_style
  attribute !logic_block
  min bits 1024
  min efficiency 5
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB36_SDP
  attribute ram_style=block ram_block
  attribute !logic_block
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB18_SDP
  attribute !ram_style
  attribute !logic_block
  min bits 1024
  min efficiency 5
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB18_SDP
  attribute ram_style=block ram_block
  attribute !logic_block
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB36_TDP
  attribute !ram_style
  attribute !logic_block
  min bits 1024
  min efficiency 5
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB36_TDP
  attribute ram_style=block ram_block
  attribute !logic_block
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB18_TDP
  attribute !ram_style
  attribute !logic_block
  min bits 1024
  min efficiency 5
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB18_TDP
  attribute ram_style=block ram_block
  attribute !logic_block
  shuffle_enable B
  make_transp
endmatch
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-04 08:35:47 -06:00			`# Virtex 6, Series 7, Ultrascale, Ultrascale Plus block RAM rules.`

Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`bram $__XILINX_RAMB36_SDP`
Added support for initialized xilinx brams 2015-04-06 10:07:10 -05:00			`init 1`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`abits 9`
			`dbits 72`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 8`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`transp 0 0`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`bram $__XILINX_RAMB18_SDP`
Added support for initialized xilinx brams 2015-04-06 10:07:10 -05:00			`init 1`
Towards Xilinx bram support 2015-01-06 16:21:52 -06:00			`abits 9`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`dbits 36`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 4`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`transp 0 0`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`bram $__XILINX_RAMB36_TDP`
Added support for initialized xilinx brams 2015-04-06 10:07:10 -05:00			`init 1`
Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`abits 10 @a10d36`
			`dbits 36 @a10d36`
			`abits 11 @a11d18`
			`dbits 18 @a11d18`
			`abits 12 @a12d9`
			`dbits 9 @a12d9`
			`abits 13 @a13d4`
			`dbits 4 @a13d4`
			`abits 14 @a14d2`
			`dbits 2 @a14d2`
			`abits 15 @a15d1`
			`dbits 1 @a15d1`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 4 @a10d36`
			`enable 1 2 @a11d18`
			`enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1`
Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`transp 0 0`
			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`bram $__XILINX_RAMB18_TDP`
Added support for initialized xilinx brams 2015-04-06 10:07:10 -05:00			`init 1`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`abits 10 @a10d18`
			`dbits 18 @a10d18`
			`abits 11 @a11d9`
			`dbits 9 @a11d9`
			`abits 12 @a12d4`
			`dbits 4 @a12d4`
			`abits 13 @a13d2`
			`dbits 2 @a13d2`
			`abits 14 @a14d1`
			`dbits 1 @a14d1`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 2 @a10d18`
			`enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`transp 0 0`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00			`# The "min bits" value were taken from:`
			`# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),`
			`# v1.14 ed., p 29-30, July, 2019.`
			`# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf`

Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`match $__XILINX_RAMB36_SDP`
Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`attribute !ram_style`
Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00			`attribute !logic_block`
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00			`min bits 1024`
Towards Xilinx bram support 2015-01-06 08:26:33 -06:00			`min efficiency 5`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`shuffle_enable B`
Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`make_transp`
Towards Xilinx bram support 2015-01-06 08:26:33 -06:00			`or_next_if_better`
			`endmatch`

Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`match $__XILINX_RAMB36_SDP`
			`attribute ram_style=block ram_block`
			`attribute !logic_block`
			`shuffle_enable B`
			`make_transp`
			`or_next_if_better`
			`endmatch`

Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`match $__XILINX_RAMB18_SDP`
Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`attribute !ram_style`
Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00			`attribute !logic_block`
Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-26 17:14:41 -06:00			`min bits 1024`
Towards Xilinx bram support 2015-01-06 08:26:33 -06:00			`min efficiency 5`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`shuffle_enable B`
Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`make_transp`
			`or_next_if_better`
			`endmatch`

Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`match $__XILINX_RAMB18_SDP`
			`attribute ram_style=block ram_block`
			`attribute !logic_block`
			`shuffle_enable B`
			`make_transp`
			`or_next_if_better`
			`endmatch`

Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`match $__XILINX_RAMB36_TDP`
Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`attribute !ram_style`
Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00			`attribute !logic_block`
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00			`min bits 1024`
Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`min efficiency 5`
			`shuffle_enable B`
			`make_transp`
Towards Xilinx bram support 2015-01-06 16:21:52 -06:00			`or_next_if_better`
Added memory_bram (not functional yet) 2014-12-31 09:53:53 -06:00			`endmatch`

Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`match $__XILINX_RAMB36_TDP`
			`attribute ram_style=block ram_block`
			`attribute !logic_block`
			`shuffle_enable B`
			`make_transp`
			`or_next_if_better`
			`endmatch`

Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`match $__XILINX_RAMB18_TDP`
Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`attribute !ram_style`
Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00			`attribute !logic_block`
Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-26 17:14:41 -06:00			`min bits 1024`
Towards Xilinx bram support 2015-01-06 16:21:52 -06:00			`min efficiency 5`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`shuffle_enable B`
			`make_transp`
Add unconditional match blocks for force RAM 2019-12-16 15:31:15 -06:00			`or_next_if_better`
			`endmatch`

			`match $__XILINX_RAMB18_TDP`
			`attribute ram_style=block ram_block`
			`attribute !logic_block`
			`shuffle_enable B`
			`make_transp`
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00			`endmatch`