2023-11-30 17:55:59 -06:00
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from __future__ import annotations
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from dataclasses import dataclass
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2023-11-28 22:34:22 -06:00
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blockram_template = """# ======================================
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2023-11-28 21:48:20 -06:00
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design -reset; read_verilog -defer ../../common/blockram.v
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2023-11-28 22:34:22 -06:00
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chparam{param_str} {top}
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2023-11-28 21:48:20 -06:00
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hierarchy -top {top}
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synth_quicklogic -family qlf_k6n10f -top {top}; cd {top}
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log ** TESTING {top} WITH PARAMS{param_str}\
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"""
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2023-11-28 22:34:22 -06:00
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blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
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2023-11-28 21:48:20 -06:00
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# TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work
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2023-11-28 22:34:22 -06:00
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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2023-11-28 21:48:20 -06:00
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# larger sizes need an extra ram
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2023-11-28 22:34:22 -06:00
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 48)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 10)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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2023-11-28 21:48:20 -06:00
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# 4096x20bit *can* fit in 3, albeit somewhat awkwardly
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2023-11-28 22:34:22 -06:00
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_*dp", ["-assert-min 3 t:TDP36K",
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"-assert-max 4 t:TDP36K"]),
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# smaller sizes can still fit in one, and assign the correct width (1, 2, 4, 8, 18 or 36)
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 24)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
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([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 4)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=4 %i"]),
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([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]),
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([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]),
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2023-11-29 17:41:03 -06:00
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# 2x asymmetric (1024x36bit write / 2048x18bit read or vice versa = 1TDP36K)
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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2023-11-29 17:41:03 -06:00
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# 4x asymmetric (1024x36bit write / 4096x9bit read or vice versa = 1TDP36K)
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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# can also use an extra TDP36K for higher width
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]),
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([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]),
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2023-11-29 17:41:03 -06:00
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# # SHIFT=0 should be identical to sync_ram_sdp
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
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2023-11-29 16:17:24 -06:00
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2023-11-29 17:41:03 -06:00
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# asymmetric memories assign different port widths on a and b ports
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=18 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=9 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=9 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=36 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=18 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=36 %i"]),
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2023-11-28 22:34:22 -06:00
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# two disjoint 18K memories can share a single TDP36K
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
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("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16),
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("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH_A", 14), ("DATA_WIDTH_A", 1),
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("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
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# but only if data width is <= 18
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([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36),
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("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]),
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2023-11-29 16:41:41 -06:00
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2023-11-28 22:34:22 -06:00
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# sharing a TDP36K sets is_split=1
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
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("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]),
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# an unshared TDP36K sets is_split=0
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]),
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2023-11-29 17:41:03 -06:00
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]),
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2023-11-29 16:41:41 -06:00
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# sharing a TDP36K sets correct port widths
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp",
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["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i",
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"-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), ("DATA_WIDTH_B", 8), ("ADDRESS_WIDTH_B", 11)], "double_sync_ram_sdp",
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["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=9 %i "
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+ "t:TDP36K a:port_a2_width=18 %i a:port_a1_width=9 %i %u",
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"-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH_A", 12), ("DATA_WIDTH_A", 4), ("DATA_WIDTH_B", 12), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp",
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["-assert-count 1 t:TDP36K a:port_a1_width=4 %i a:port_a2_width=18 %i "
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+ "t:TDP36K a:port_a2_width=4 %i a:port_a1_width=18 %i %u",
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"-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH_A", 13), ("DATA_WIDTH_A", 2), ("DATA_WIDTH_B", 1), ("ADDRESS_WIDTH_B", 14)], "double_sync_ram_sdp",
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["-assert-count 1 t:TDP36K a:port_a1_width=2 %i a:port_a2_width=1 %i "
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+ "t:TDP36K a:port_a2_width=2 %i a:port_a1_width=1 %i %u",
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"-assert-count 1 t:TDP36K"]),
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2023-11-28 21:48:20 -06:00
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]
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2023-11-30 17:55:59 -06:00
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sim_template = """\
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cd
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read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
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read_verilog <<EOF
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`define MEM_TEST_VECTOR {mem_test_vector}
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`define UUT_SUBMODULE \\
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{uut_submodule}
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EOF
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read_verilog -defer -formal mem_tb.v
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chparam{param_str} -set VECTORLEN {vectorlen} TB
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hierarchy -top TB -check
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proc
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sim -clock clk -n {vectorlen} -assert
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"""
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sync_ram_sdp_submodule = """\
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sync_ram_sdp #(\\
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.ADDRESS_WIDTH(ADDRESS_WIDTH),\\
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.DATA_WIDTH(DATA_WIDTH)\\
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) uut (\\
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.clk(clk),\\
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.address_in_r(ra_a),\\
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.data_out(rq_a),\\
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.write_enable(wce_a),\\
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.address_in_w(wa_a),\\
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.data_in(wd_a)\\
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);\
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"""
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2023-11-30 22:00:15 -06:00
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sync_ram_tdp_submodule = """\
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sync_ram_tdp #(\\
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.ADDRESS_WIDTH(ADDRESS_WIDTH),\\
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.DATA_WIDTH(DATA_WIDTH)\\
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) uut (\\
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.clk_a(clk),\\
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.clk_b(clk),\\
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.write_enable_a(wce_a),\\
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.write_enable_b(wce_b),\\
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.read_enable_a(rce_a),\\
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.read_enable_b(rce_b),\\
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.addr_a(ra_a),\\
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.addr_b(ra_b),\\
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.read_data_a(rq_a),\\
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.read_data_b(rq_b),\\
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.write_data_a(wd_a),\\
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.write_data_b(wd_b)\\
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);\
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"""
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2023-11-30 17:55:59 -06:00
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@dataclass
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class TestClass:
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params: dict[str, int]
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top: str
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assertions: list[str]
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test_steps: None | list[dict[str, int]]
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test_val_map = {
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"rce_a": "rce_a_testvector",
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"ra_a": "ra_a_testvector",
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"rq_a": "rq_a_expected",
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"wce_a": "wce_a_testvector",
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"wa_a": "wa_a_testvector",
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"wd_a": "wd_a_testvector",
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"rce_b": "rce_b_testvector",
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"ra_b": "ra_b_testvector",
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"rq_b": "rq_b_expected",
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"wce_b": "wce_b_testvector",
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"wa_b": "wa_b_testvector",
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"wd_b": "wd_b_testvector",
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}
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sim_tests: list[TestClass] = [
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TestClass( # basic SDP test
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# note that the common SDP model reads every cycle, but the testbench
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# still uses the rce signal to check read assertions
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params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36},
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top="sync_ram_sdp",
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assertions=[],
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test_steps=[
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{"wce_a": 1, "wa_a": 0x0A, "wd_a": 0xdeadbeef},
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{"wce_a": 1, "wa_a": 0xBA, "wd_a": 0x5a5a5a5a},
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{"wce_a": 1, "wa_a": 0xFF, "wd_a": 0},
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{"rce_a": 1, "ra_a": 0x0A},
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{"rq_a": 0xdeadbeef},
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{"rce_a": 1, "ra_a": 0xFF},
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{"rq_a": 0},
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]
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),
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2023-11-30 22:00:15 -06:00
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TestClass( # SDP read before write
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params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16},
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top="sync_ram_sdp",
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assertions=[],
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test_steps=[
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{"wce_a": 1, "wa_a": 0xA, "wd_a": 0x1234},
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{"wce_a": 1, "wa_a": 0xA, "wd_a": 0x5678, "rce_a": 1, "ra_a": 0xA},
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{"rq_a": 0x1234, "rce_a": 1, "ra_a": 0xA},
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{"rq_a": 0x5678},
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]
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),
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TestClass( # basic TDP test
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# note that the testbench uses ra and wa, while the common TDP model
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# uses a shared address
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params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36},
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top="sync_ram_tdp",
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assertions=[],
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test_steps=[
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{"wce_a": 1, "ra_a": 0x0A, "wce_b": 1, "ra_b": 0xBA,
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"wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a},
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{"wce_a": 1, "ra_a": 0xFF,
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"wd_a": 0},
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{"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A},
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{"rq_a": 0xdeadbeef, "rq_b": 0xdeadbeef},
|
|
|
|
{"rce_a": 1, "ra_a": 0xFF, "rce_b": 1, "ra_b": 0xBA},
|
|
|
|
{"rq_a": 0, "rq_b": 0x5a5a5a5a},
|
|
|
|
]
|
|
|
|
),
|
|
|
|
TestClass( # TDP with truncation
|
|
|
|
params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16},
|
|
|
|
top="sync_ram_tdp",
|
|
|
|
assertions=[],
|
|
|
|
test_steps=[
|
|
|
|
{"wce_a": 1, "ra_a": 0x0F, "wce_b": 1, "ra_b": 0xBA,
|
|
|
|
"wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a},
|
|
|
|
{"wce_a": 1, "ra_a": 0xFF,
|
|
|
|
"wd_a": 0},
|
|
|
|
{"rce_a": 1, "ra_a": 0x0F, "rce_b": 1, "ra_b": 0x0A},
|
|
|
|
{"rq_a": 0, "rq_b": 0x00005a5a},
|
|
|
|
]
|
|
|
|
),
|
|
|
|
TestClass( # TDP read before write
|
|
|
|
# note that the testbench uses rce and wce, while the common TDP model
|
|
|
|
# uses a single enable for write, with reads on no write
|
|
|
|
params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36},
|
|
|
|
top="sync_ram_tdp",
|
|
|
|
assertions=[],
|
|
|
|
test_steps=[
|
|
|
|
{"wce_a": 1, "ra_a": 0x0A, "wce_b": 1, "ra_b": 0xBA,
|
|
|
|
"wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a},
|
|
|
|
{"wce_a": 1, "ra_a": 0xBA, "rce_b": 1, "ra_b": 0xBA,
|
|
|
|
"wd_a": 0xa5a5a5a5},
|
|
|
|
{ "rq_b": 0x5a5a5a5a},
|
|
|
|
{"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A},
|
|
|
|
{"rq_a": 0xdeadbeef, "rq_b": 0xdeadbeef},
|
|
|
|
{ "rce_b": 1, "ra_b": 0xBA},
|
|
|
|
{ "rq_b": 0xa5a5a5a5},
|
|
|
|
]
|
|
|
|
),
|
2023-11-30 17:55:59 -06:00
|
|
|
]
|
|
|
|
|
|
|
|
for (params, top, assertions) in blockram_tests:
|
|
|
|
sim_test = TestClass(
|
|
|
|
params=dict(params),
|
|
|
|
top=top,
|
|
|
|
assertions=assertions,
|
|
|
|
test_steps=None
|
|
|
|
)
|
|
|
|
sim_tests.append(sim_test)
|
|
|
|
|
|
|
|
i = 0
|
|
|
|
j = 0
|
|
|
|
max_j = 16
|
|
|
|
f = None
|
|
|
|
for sim_test in sim_tests:
|
|
|
|
# format params
|
|
|
|
param_str = ""
|
|
|
|
for (key, val) in sim_test.params.items():
|
|
|
|
param_str += f" -set {key} {val}"
|
|
|
|
|
|
|
|
# resolve top module wildcards
|
|
|
|
top_list = [sim_test.top]
|
|
|
|
if "*dp" in sim_test.top:
|
|
|
|
top_list += [
|
|
|
|
sim_test.top.replace("*dp", dp_sub) for dp_sub in ["sdp", "tdp"]
|
|
|
|
]
|
|
|
|
if "w*r" in sim_test.top:
|
|
|
|
top_list += [
|
|
|
|
sim_test.top.replace("w*r", wr_sub) for wr_sub in ["wwr", "wrr"]
|
|
|
|
]
|
|
|
|
if len(top_list) > 1:
|
|
|
|
top_list.pop(0)
|
|
|
|
|
|
|
|
# iterate over string substitutions
|
|
|
|
for top in top_list:
|
|
|
|
# limit number of tests per file to allow parallel make
|
|
|
|
if not f:
|
|
|
|
fn = f"t_mem{i}.ys"
|
|
|
|
f = open(fn, mode="w")
|
|
|
|
j = 0
|
|
|
|
|
|
|
|
# output yosys script test file
|
|
|
|
print(
|
|
|
|
blockram_template.format(param_str=param_str, top=top),
|
|
|
|
file=f
|
|
|
|
)
|
|
|
|
for assertion in sim_test.assertions:
|
|
|
|
print("select {}".format(assertion), file=f)
|
|
|
|
print("", file=f)
|
|
|
|
|
|
|
|
# prepare simulation tests
|
|
|
|
test_steps = sim_test.test_steps
|
|
|
|
if test_steps:
|
|
|
|
if top == "sync_ram_sdp":
|
|
|
|
uut_submodule = sync_ram_sdp_submodule
|
2023-11-30 22:00:15 -06:00
|
|
|
elif top == "sync_ram_tdp":
|
|
|
|
uut_submodule = sync_ram_tdp_submodule
|
2023-11-30 17:55:59 -06:00
|
|
|
else:
|
|
|
|
raise NotImplementedError(f"missing submodule header for {top}")
|
|
|
|
mem_test_vector = ""
|
|
|
|
for step, test in enumerate(test_steps):
|
|
|
|
for key, val in test.items():
|
|
|
|
key = test_val_map[key]
|
|
|
|
mem_test_vector += f"\\\n{key}[{step}] = 'h{val:x};"
|
|
|
|
print(
|
|
|
|
sim_template.format(
|
|
|
|
mem_test_vector=mem_test_vector,
|
|
|
|
uut_submodule=uut_submodule,
|
|
|
|
param_str=param_str,
|
|
|
|
vectorlen=len(test_steps) + 2
|
|
|
|
), file=f
|
|
|
|
)
|
|
|
|
# simulation counts for 2 tests
|
|
|
|
j += 1
|
|
|
|
|
|
|
|
# increment test counter
|
|
|
|
j += 1
|
|
|
|
if j >= max_j:
|
|
|
|
f = f.close()
|
|
|
|
i += 1
|
|
|
|
|
|
|
|
if f:
|
|
|
|
f.close()
|