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yosys/tests/arch/xilinx/fsm.ys

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Share common tests
2019-10-18 05:19:59 -05:00
read_verilog ../common/fsm.v
remove not needed top module
2019-10-04 02:41:45 -05:00
hierarchy -top fsm
Add smoke tests to tests/xilinx
2019-09-10 00:08:03 -05:00
proc
flatten
Fixed tests
2019-11-11 08:41:33 -06:00
xilinx: Initial support for LUT4 devices. Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
2020-02-03 09:19:24 -06:00
design -save orig
Make test without iopads
2019-12-28 09:22:24 -06:00
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
Fixed tests
2019-11-11 08:41:33 -06:00
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
Add smoke tests to tests/xilinx
2019-09-10 00:08:03 -05:00
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
remove not needed top module
2019-10-04 02:41:45 -05:00
cd fsm # Constrain all select calls below inside the top module
Fix tests
2020-01-10 07:48:01 -06:00
stat
Add smoke tests to tests/xilinx
2019-09-10 00:08:03 -05:00
select -assert-count 1 t:BUFG
xilinx: Improve flip-flop handling. This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
2019-11-20 23:30:06 -06:00
select -assert-count 4 t:FDRE
select -assert-count 1 t:FDSE
select -assert-count 1 t:LUT2
this one is fine
2020-01-10 08:20:50 -06:00
select -assert-count 3 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
xilinx: Initial support for LUT4 devices. Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
2020-02-03 09:19:24 -06:00
design -load orig
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 3 t:LUT3
select -assert-count 6 t:LUT4
select -assert-count 6 t:MUXF5
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D