2019-10-18 05:19:59 -05:00
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read_verilog ../common/fsm.v
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2019-10-04 02:41:45 -05:00
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hierarchy -top fsm
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2019-09-10 00:08:03 -05:00
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proc
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flatten
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2019-11-11 08:41:33 -06:00
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2019-12-28 09:22:24 -06:00
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
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2019-11-11 08:41:33 -06:00
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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2019-09-10 00:08:03 -05:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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2019-10-04 02:41:45 -05:00
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cd fsm # Constrain all select calls below inside the top module
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2020-01-10 07:48:01 -06:00
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stat
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2019-09-10 00:08:03 -05:00
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select -assert-count 1 t:BUFG
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2019-11-20 23:30:06 -06:00
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select -assert-count 4 t:FDRE
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select -assert-count 1 t:FDSE
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select -assert-count 1 t:LUT2
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2020-01-10 07:48:01 -06:00
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select -assert-count 2 t:LUT3
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select -assert-count 4 t:LUT5
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select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D
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