* Change: In GCell::stepNetDesaturate(), never move up a segment in
non-preferred direction as they are usually attached to terminals,
so they won't reduce the GCell density anyway.
* Change: In LayerAssign::RpsInRow::slacken(), do not slacken horizontals
from M1 vertical terminals when they are tall enough. Arbitrarily
choose above 6 H-tracks (should be made a configuration parameter).
* Change: In DataNegociate::update(), when processing perpandicular,
we were taking into account "fixed axis" even when they were
reduced (so not in tracks). Now do not.
In CoreToChip, the "iolib" I/O pad library an alternative to the "cmos"
one. "cmos" uses the pxlib library while iolib uses a symbolic abstract
version of the C4M (real) I/O pad.
The initialization is a bit split as the "cmos" library are part of
Alliance, while "iolib" is in alliance-check-toolkit. So "iolib" is
added at designflow.technos.setupCMOS().
Setup additional configuration parameter directly in:
core2chip.niolib.CoreToChip.__init__().
* Bug: In CRL/technos.node180.gf180mcu_c4m.iolib.py, remove the VDD and
VSS ring terminals in the pad as only *some* of the have it.
Assume that it is a bug from GF. The power rail will still be ok
as it connect by abutment (with the filler & other I/O pads).
* New: In cumulus.plugins.block.configuration.py, added support for
iterable I/O pad specifications in ioPads argument.
* New: In cumulus.plugins.core2chip.core2chip.py, add support for
any number of control signals on I/O pads. Not fully implemented
yet, as we only allow to hard-wire them either to one or zero.
Raise an error if _connect() fails to find a master net, so
we don't fail strangely later...
* New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin
for Yosys.
* Fix: In designflow.svase, remove the transient file "slang-args.txt".
* Change: In designflow.yosys, remove the direct SystemVerilog support
that is delegated to Surelog and just load the resulting UHDM.
Merge with yosysnp and automatically detect if we can load the
Python plugin or go through a script.
* New: In designflow.yosys, add support to load SystemVerilog with the
synlig plugin (CHIPS Alliance).
Integrate back the "non-Python" version of the task. Now switch
automatically between Python & Non-Python based on the availability
of the plugin. Also select between "yosys" & "yowasp-yosys".
* Change: In svase & sv2v, suppress the requirement of the *first*
dependency file to be used as the default target. Now use the
"top module" argument.
Rob Taylor
Jean-Paul Chaput
Gabriel Gouvine