* Change: In GCell::stepNetDesaturate(), never move up a segment in
non-preferred direction as they are usually attached to terminals,
so they won't reduce the GCell density anyway.
* Change: In LayerAssign::RpsInRow::slacken(), do not slacken horizontals
from M1 vertical terminals when they are tall enough. Arbitrarily
choose above 6 H-tracks (should be made a configuration parameter).
* Change: In DataNegociate::update(), when processing perpandicular,
we were taking into account "fixed axis" even when they were
reduced (so not in tracks). Now do not.
In CoreToChip, the "iolib" I/O pad library an alternative to the "cmos"
one. "cmos" uses the pxlib library while iolib uses a symbolic abstract
version of the C4M (real) I/O pad.
The initialization is a bit split as the "cmos" library are part of
Alliance, while "iolib" is in alliance-check-toolkit. So "iolib" is
added at designflow.technos.setupCMOS().
Setup additional configuration parameter directly in:
core2chip.niolib.CoreToChip.__init__().
* Bug: In CRL/technos.node180.gf180mcu_c4m.iolib.py, remove the VDD and
VSS ring terminals in the pad as only *some* of the have it.
Assume that it is a bug from GF. The power rail will still be ok
as it connect by abutment (with the filler & other I/O pads).
* New: In cumulus.plugins.block.configuration.py, added support for
iterable I/O pad specifications in ioPads argument.
* New: In cumulus.plugins.core2chip.core2chip.py, add support for
any number of control signals on I/O pads. Not fully implemented
yet, as we only allow to hard-wire them either to one or zero.
Raise an error if _connect() fails to find a master net, so
we don't fail strangely later...
* New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin
for Yosys.
* Fix: In designflow.svase, remove the transient file "slang-args.txt".
* Change: In designflow.yosys, remove the direct SystemVerilog support
that is delegated to Surelog and just load the resulting UHDM.
Merge with yosysnp and automatically detect if we can load the
Python plugin or go through a script.
* New: In designflow.yosys, add support to load SystemVerilog with the
synlig plugin (CHIPS Alliance).
Integrate back the "non-Python" version of the task. Now switch
automatically between Python & Non-Python based on the availability
of the plugin. Also select between "yosys" & "yowasp-yosys".
* Change: In svase & sv2v, suppress the requirement of the *first*
dependency file to be used as the default target. Now use the
"top module" argument.
Even when we were creating Contacts of null width or height, they where
bumped to the minimal size by the constructor, hence bits sticking out
at the end with Gds PATHTYPE 4. Now, allow null size for non-composite
(which contains a cut) and non-cut Contacts.
* Fix: In GdsParser::readStructure(), always use the bounding box as
abutment box if the later is empty (case of small sub-components).
This was making the sub-component seemingly diseapear in the
viewer...
* Fix: In GdsParser::xyToPath(), slight change in xadjust & yadjust.
* Change: In Contact::create(), force the contact width and height to
the minimal size *only* if it's a composite layer *or* a basic layer
of "cut" material.
* Bug: In cumulus.plugins.chips.pads.Side._placePads(), when pads have
positions they must be reorder *prior* to recomputing the pad
final position? In order to avoid overlap and ensuring that they are
on pitch, according to the I/O pad routing gauge.
* Bug: In GdsParser::readStructure(), the Gds::Layer_0_IsBoundary flag
was not taken into account. The abutment box was always forced to
the bounding box, resulting in incorrect cell size (and placement).
Rob Taylor
Jean-Paul Chaput
Gabriel Gouvine