* Bug: In Viewer::SelectionPopup(), the window attribute
Qt::WA_DeleteOnClose was *not* cleared. So the window was deleted
after first use while it was though staying allocated.
Again, generating weird crashes.
Took the occasion to slightly redesign the behavior to select
and highlight individual components.
* Bug: In Isobar3::PyTypeManager, the accessors _getCppTypeName() and
_getPyTypeName() where returning string *by value*, hence, short
lived copies.
But, in _setupPyType() and _addToModule(), as we interface with
the Python/C API, we extract the c_str(). Which where removed as
we used temporary objects. Leading to memory corruption and weird
crashes.
Now returns "const string&" so the c_str() stays allocated.
* Bug: In CellWidget::DrawingQuery::drawGo(), the display condition was
wrong, it was requiring *both* width & height to be above the display
threshold. Either one is sufficient to activate the display.
Was causing the selective diseapearance of gates at low zoom level
and printed version.
* Change: In CellPrinter, force the display threshold to one pixel in it's
internal CellWidget used for printing.
* Bug: In Katana::DataNegociate::update(), when computing the length of
source & target extension on a perpandicular segment, must use the
extensions of the *directly* connected AutoSegment (the baseSegment)
and not the canonical one that may be different, so with unrelated
extensions.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), the RoutingPads
for the input and output of the buffer where sometimes put too
close from each others, giving the pitch of the vertical tracks.
Now shift one pitch left the vertical branchs of the H-Tree.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), also shift down
one pitch the horizontal branch, due to track rounding they *may*
end up on the same track, generating a short.
* Bug: In Anabatic::layerAssign(), during the step of desaturation of
GCells that contains too much terminals (i.e. lot of *local*
congestion), the desaturation threshold was har-coded to 8.
Wich is fine for symbolic cmos but way too low for Flexlib.
End result was that most straight wires where moved towards
the upper layers, creating congestion (imbalance of layer
densities).
Now the parameter:
* "anabatic.saturateRp" (default value:8) is correctly taken
into account.
* Fix: In Manipulator::avoidBlockage(), the dedicated function to check if
there is an obstacle in the way of a non-prefered routing wire (done
for metal2 connecting to terminals only) was too naive.
We were checking the tracks for obstacles crossing exactly the axis
of the segment. And for near-miss this is not enough. Now check on
the whole x-span to be used by the segment.
Code borrowed and simplified from Track::addOverlapcost().
* Change: In Manipulator::moveUp(), the default value for the extra
reservation allowing a long wire to move up need to be customized
for Flexlib/StdCellLib (allow successful routing of ChipFlow/MPW4).
Add two new configuration parameters to katana:
* "katana.longWireUpThresold1" : the length, expressed in number
of *slice height* above which a global wire is considered a
*long* wire (not close interconnect).
* "katana.longWireUpReserve1" : the extra number of free tracks
that must remains free in the up layer after the move up,
in each GCell traversed by the wire. Expressed in number of
tracks, but can be non-integer (float, for instance: 1.5).
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), to avaid tracks too
close to an offgrid obstacle in the preferred routing direction, we
expand the width/height of the segment by one pitch. BUT it seems to
still be too close for Flexlib and StdCellLib, so there is an ad-hoc
patch based on the *name* of the cell library. Update it to take
"StdCellLib" into account.
NOTE: This is likely to explain why we still got overlap in the
track coherency check in very rare occasions.
* Bug: In Katana::DataNegociate::update(), when computing the allowed
free interval for the segment axis deduced from the perpandicularly
connex segments, we account for the extension of the connecting
VIA. Those extension varies according to the kind of VIA and are
given by getExtensionCap().
We were accounting for the source & target extension VIA on the
parallel segments, assuming that source/target would not swap when
the perpandicular is moved. Which is *not* true.
Now account for the extension of the *connecting* VIA on all ends.
* Change: In AutoSegment::getTopologicalInfos(), enrich the list of
perpandicularly connected segment with wether they are connex by
their *source* or *target* contact. Mainly to be used by
DataNegociate::update().
* Change: In cumulus/plugins/core2chip, instead of the user providing
an explicit mapping towards the harness I/O pins, we expect that
the core block must have I/O pins with names matching thoses of
the harness. That way, connections are automatically made.
* Change: In cumulus/plugins/block/htree, if the root signal of the
H-Tree is a bit from a vector (like "io_in(0)"), then remove the
vector index notation on all the stem name of all the sub-nets.
Done by the unbitify() function: "io_in(0)" => "io_in_bit0".
* Change: In EtesianEngine::_postCreate(), issue a warning if the list of
feeds is empy (configuration: "cfg.etesian.feedNames").
* New: Add a FeedCeels::getFeedByWidth() method to get feeds by their
width in DbU::Unit and not only pitches.
* Change: In Placement::Slice::fillHole(), invert the tie filling and
feeds filling stage. Now we first try to fill the row hole with
feeds, using the widest first, and if they are not configured or
too wide, use the tie.
As the tie *should* also be integrated in the feed list, we may
suppress altogether the fallback tie filling step. Keep it for now.
* Change: In Placement::slice::createDiodeUnder(), the inserted diode
*may* be smaller than the feed it replace. So, in this case, add
a complementary feed to fill the gap.
NOTE 1: Out of lazyness, we add only *one* complementary filler
cell. So there *must* be one of a width wich correspond
exactly to the difference between the original feed and
the diode. Otherwise, gap will remains.
NOTE 2: With wider feed cells, they may cross the GCell border.
But we must insert the diode under the GCell, otherwise
the global routing will be defective. So, for now, reject
feeds that cross the boundary. Must be done more smartly
by inserting the diode over the left or right side of
the feed.
* Change: In AnabaticEngine::setupPrerouteds(), take into account the
number of Pins. Now consider a net containing multiple Pins and, at most,
one segment as *non-routed".
This case may specifically happens for nets with pins on the north
and east side, which are slightly *inside* the abutment box (to be
seen by the router) and draw with them their *outside* direct
connection wire.
* Bug: In cumulus/plugins.chip.CoreWire, no longer put the north or
east side external Pin *exacyly* on the abutment box but *one pitch*
inside so they are correctly seens by the P&R (must be *inside*
the area of a GCell).
It is now possible to automatically nest a core block inside a harness
frame, like we do for an ordinary chip whith I/O pads. The DEF harness
file "user_project_wrapper.def" must be made available though the block
configuration variable:
conf.cfg.harness.path = './user_project_wrapper.def'
A first small example is given in:
alliance-check-toolkit/benchs/counter/sky130_c4m
The harness layout is stripped from it's native power grid (but keep
the power ring). I/O pad information in block/configuration is
slightly "bent* to manage pins instead of complete I/O pads.
* Bug: In cumulus/plugins.block.Block.setupAb(), the routingBb was not
set up when working in chip mode. Now set (to the corona AB).
* Change: In cumulus/plugins.chip.__init__, move there the CoreWire
class (from chip/pads.py) so it can be shared with the harness
version of pads.py.
* Change: In cumulus/plugins.chip.powerplane, compute the intersection
between the vertical supply stripes and the deep horizontal power
lines in a smarter fashion, so two (or more) vertically contiguous
BigVias are merged into one (two BigVia side by side where causing
mimimal spacing distance violation on the cut in Sky130).
* New: In Anabatic::AutoSegment::create(), allow the created segment to
be in any supported routing layer, and not only the bottom H & V.
Modifications impact the *two* overload of the function.
* Change: In Anabatic::NetBuilderHV::doRp_AutoContacts(), for punctual
METAL1, the protection has to be in METAL2. Bump the layer depth
to correctly use the updated verstion of AutoSegment::create().
* Change: In AnabaticEngine::checkPlacement(), for the Pin, check that
it's layer is in the routing gauge before anything else.
* New: In Katana::NegociateWindow::createTrackSegment(), if the track
nearest the segment axis (refTrack) do not exists, call a
breakpoint just before crashing.
* Bug: In CRL::BlifParser::Model CTOR, forgot to set the direction
on auto-generated power supply global nets. So they were put
in "linkage" in the VST files.
* New: In CRL::DefImport, add specific support for the Sky130/Caravel
harness "user_project_wrapper".Mainly:
- Do not fuse together "io_in" and "io_out" as a single net as
they should (according to the DEF). So we can connect separately
on each of them. We only allow one port for each net, as in VHDL.
* Bug: In CRL::MeasureSet::toStringHeaders(), check and issue a warning
if a measure label ends with a "." (dot).
* Change: In CRL::ToolEngine::getMeasure(), return the data measure
by pointer instead of by reference (easier to manipulate afterwards).
* New: In EtesianEngine::place(), add the placement runtime (under label
"placeT") to the measure set.
* New: In KatanaEngine::dumpMeasures(), add the Etesian runtime to the
set of measures.
* New: In cumulus/plugins.block.congiguration: New PowersConf config
sub-object to store characteristics of the "powmid_x0" cell.
The name of the Cell with which to build the vertical power
rails is given though the cfg parameter:
"cfg.etesian.cell.power"
* New: In cumulus/plugins.block.spares, add support for creating
vertical power lines along with the buffers pools of the H-Trees.
At most, one vertical power rail will be put exactly at the right
edge of the buffer pool of each leaf QuadTree. We can reduce that
number, using the parameter:
"cfg.block.vRailsPeriod = N"
Which give the ratio to use (one over N QuadTree leaf).
WARNING: This may not work if the QuadTree is "dented" not in a
corner but in the *middle* of the side. Needs to be
improved and/or checked.
WARNING: We are partially duplicating the informations pertaining
to the Alliance catalog (stored in the Catalog property)
directly into the Cell. This is needed for Flexlib which
is not using the Alliance loading mechanim. Ideally the
Catalog information should be moved into the Cell.
* New: In Cell, add new state flags Diode, PowerFeed (in addition to
Pad & Feed).
Export flags setter/getter to Python. For Flexlib usage.
* Change: In AllianceFramework::getInstancesCount(), correctly skip
Diode & Feeds based on Cell flags. Those flags must correctly
be set in the various Flexlib_fix.py scripts.
* Bug: In Track::repair(), when closing a same net gap, the amount the
"right" segment duSource must be shifted left was incorrectly
computed in some instances.
The previous calculation was assuming that the right edge of the
gap was at the exact same position than the source extension.
But when there is a non-preferred direction connected to it, this
is wrong. Now compute the delta accounting for a difference
between the right edge of the gap and the source extension.
NOTE: Due to Python pathes, the NDA.common is *not* seen, even by NDA
protected configuration. They are using the non-NDA one. No harm
in that, just need to be known...
* New: In AllianceFramework::getInstancesCount(), add a flag TerminalNetlist
to stop recursion on "terminal for netlist" instance level. This is to
avoid counting physical only or non-routed instances inside hard macros,
like SRAM blocks. This was leading to an overstimation of the "size"
in number of gates of the routing problem.
* Change: In KatanaEngine CTOR, call for the terminal for netlist number of
gates...
* New: In DeepNet, add an DeepNet::Uplink property on the HyperNet
root net Occurrence so we have a direct two-way link between
the top (flattened net) and the root of the HyperNet.
Down link is ensured by the Occurrence, up link by the Uplink
property.
* Change: In Cell::getDeepNet(), now use the DeepNet Uplink property
instead of looping over *all* top nets. This was the cause of the
terrific slow down in PowerRails, especially on flatteneds designs.
* New: In AnabaticEngine::printMeasures(), re-enable runtime & memory
footprint in measurements.
* Bug: In Anabatic::AutoSegment CTOR, correct computation of the initial
number of global segments. We were relying on the "global" flag,
which is *not* set at this stage. Now compare source and target
GCells.
* New: In KatanaEngine::runGlobalRouter(), store H-ovE & V-ovE in
measurements.
* New: In KatanaEngine CTOR, add the number of gates (flattened) to
the measurments.
* New: In KatanaEngine::runNegociate(), add the number of GCells to
the measurements.
* Change: In KatanaEngine::printCompletion(), compute the wirelengths
in either lambdas (symbolic) or *nanometers* (real).
* New: In cumulus/plugins.block.Block, add a setting to request the
Katana measurements dumping: "cfg.katana.dumpMeasures"
* Bug: In all CMakeLists.txt, it seems I was doing a worng use of
target_link_library(). No longer add dependencies to the C++ base
library but instead either to the Python associated module or
to the final binaries. This was inderectly causing the linking
problem related to Python (which was a misdirection).
* Bug: Typo in FindLibexecinfo.cmake, do not use FindLib[E]xecinfo.
* Change: In CRL/ccore/CMakeLists.txt, activate SKIP_AUTOMOC on
bison/flex generated files.
* Bug: In viewer/PyHApplication, do not delete the C++ object in
the Python destroy method.
gatecat
Jean-Paul Chaput
Gabriel Gouvine