riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,180 Commits 18 Branches 8 Tags 96 MiB
Commit Graph

3180 Commits

Author SHA1 Message Date
Jean-Paul Chaput bcdda98806 Duplicated ".spi" targets in pnrcheck designflow. 2023-11-23 12:38:04 +01:00
Jean-Paul Chaput db444314c8 Do not protect with TrackMarkers M2 RoutingPads. 2023-11-23 12:38:04 +01:00
Jean-Paul Chaput 4884929370 Don't connect with M2 on M3 RoutingPads. 2023-11-23 12:38:04 +01:00
Jean-Paul Chaput 8b40b6ecae Fix the loading of initHook.py, use Python loading mechanism directly. 2023-11-23 12:38:04 +01:00
Jean-Paul Chaput b17222e049 New rule "install_docs" to build the documentation. 2023-11-23 12:38:04 +01:00
Jean-Paul Chaput 8159ebde1d One less level in the left menu (was too wide). 2023-11-23 12:38:04 +01:00
Jean-Paul Chaput fa4fce01e9 Install Oroshi doc in the right place. 2023-11-23 12:38:04 +01:00
Jean-Paul Chaput 0ef3f64f5a Rename tabs.css into custom_tabs.css to avoid doxygen overwrite. 2023-11-23 12:38:04 +01:00
Rob Taylor fbbcb4f8cf tweak readme 2023-11-18 17:31:17 +00:00
Rob Taylor 3163b5ee45 Fix some typos in documentation and a number of whitespace issues 2023-11-18 17:31:17 +00:00
Rob Taylor 205a21aaf0 Add github pages workflow 2023-11-18 17:31:17 +00:00
Rob Taylor 82af38216d Fix header character usage - crashes with newer docutils 2023-11-18 17:31:17 +00:00
Rob Taylor 6ff5cf3e3c Add meson build infrastructure for pelican webpage 2023-11-18 17:31:17 +00:00
Robert Taylor 95c0ca3d8d Update requirements and add missing pdm.lock 2023-11-18 17:31:17 +00:00
Rob Taylor 6f3e6ca6d3 Add meson build infrastructure for doxygen based content 2023-11-18 17:31:17 +00:00
Robert Taylor e0969b8ca9 Remove generated doc files 2023-11-18 17:31:17 +00:00
Rob Taylor fc93118fd3 Update doxyfiles to latest doxygen 2023-11-18 17:31:17 +00:00
Ross Motley b2f7aa7aab Failures in PyPi uploads should fail workflows 2023-11-16 21:58:45 +00:00
Ross Motley 885b4b1a35 Fix meson README link 2023-11-14 14:19:21 +00:00
Ross Motley 8bcc10ed02 Fix _PDM link in README 2023-11-14 14:19:21 +00:00
lanserge 500d4446c2
Filter out redundant plugs that have no connection inside cell while export Verilog netlist. (#84) 
Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io>
 2023-11-10 13:56:58 +00:00
Gabriel Gouvine 8e5db42aff Update Coloquinte version to 0.4.1 (bug fixes + area update infrastructure) 2023-11-07 10:45:52 +01:00
Gabriel Gouvine 7a0602fcbd Extend .gitignore 2023-11-03 13:26:16 +01:00
Gabriel Gouvine c00dbe810c Update coloquinte version for slightly better results and easier debugging 2023-11-03 13:26:16 +01:00
Gabriel Gouvine 97124f582f Simple clang format file 2023-11-03 13:26:16 +01:00
Gabriel Gouvine 3757f64830 Introduce complete ripup functions for the router 2023-11-03 13:26:16 +01:00
Gabriel Gouvine 339ed4f9ff Introduce flags for placement callbacks in Etesian 2023-11-03 13:26:16 +01:00
Gabriel Gouvine d27cc8b956 Split callback in Etesian to allow for derived placer classes 2023-11-03 13:26:16 +01:00
lanserge 44ce8dd162
Added Verilog driver for netlist export (#80) 
CRL.Verilog.save(cell, 0) -> exports cell into Verilog netlist file

Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io>
 2023-11-02 14:09:33 +00:00
Jean-Paul Chaput f840563712 Update the doc for gitlab & github. 2023-10-20 10:52:58 +02:00
Jean-Paul Chaput 2ffbdbf3eb In BlockConf.useHTree(), must set the useClockTree flag (for chip mode). 2023-10-20 10:52:58 +02:00
Jean-Paul Chaput 9bf25c28bf In designflow.technos.setupCMOS(), more relaxed clock name pattern. 2023-10-20 10:52:58 +02:00
Jean-Paul Chaput a07fa9a1ec In designflow.blif2vst, add the ".spi" file to the target list (for cleanup). 2023-10-20 10:52:58 +02:00
Jean-Paul Chaput c4f65be096 Add a prefix to GDS sub-cell isolated in a "per cell" library. 
The GDS file write all the cell names (SREF) in one namespace, so cells
with identical names, coming from different libraries may clash. When
a GDS is read *and* contains sub-cell, we isolate them in a sub-library,
but we must *also* give the cells in them unique names, we prefix by
the library name (which in turn is the top cell name).
 2023-10-20 10:52:58 +02:00
Jean-Paul Chaput 93cc7cd178 Protect Python accessor wrapper from C++ thrown exceptions. 2023-10-20 10:52:58 +02:00
Jean-Paul Chaput a665a1bcfc The upper routing layer in gf180mcu is Metal5, not MetalTop (power). 2023-10-20 10:52:58 +02:00
Jean-Paul Chaput d532bb563f Use Ubuntu distributed Yosys instead of yowasp-yosys. 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput e43d0d2ef0 When using HTree in a chip in CMOS, must also set useClockTree flag. 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput 97bad74412 And ninja build is now also missing! 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput fb928b1b75 Missing cmake dependency in regression flow (?). 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput 8ddb323e86 Support for the github directory layout. 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput 11070af489 Forgotten backslash in regression.yml 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput 87840d802d meson and yowasp-yosys must be installed through pip. 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput b97c6fdc59 Update regession test for the new install tree scheme. 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput b9a7992339 Correct the nighlty build directory. 2023-10-18 16:58:12 +01:00
Jean-Paul Chaput a680ec0575 Makefile is only for LIP6. Update nightly build. 2023-10-18 16:58:12 +01:00
Rob Taylor 4e62c8689a Merge INSTALL.rst into README 2023-10-18 16:58:12 +01:00
Rob Taylor 98186cacc2 Update INSTALL.rst for a decent developer experience 2023-10-18 16:58:12 +01:00
Rob Taylor 82c2236b89 Set up pdm environment to work nicely 2023-10-18 16:58:12 +01:00
Rob Taylor 6e4ea95aaf Update README for pypi install 2023-10-18 16:58:12 +01:00