Added Verilog driver for netlist export (#80)
CRL.Verilog.save(cell, 0) -> exports cell into Verilog netlist file Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io>
This commit is contained in:
lanserge
GitHub
parent
f840563712
commit
44ce8dd162
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@ -106,6 +106,8 @@
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spice/SpiceParser.cpp
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spice/SpiceDriver.cpp
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)
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set ( verilog_cpps verilog/VerilogDriver.cpp
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)
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set ( bookshelf_cpps bookshelf/BookshelfParser.cpp
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bookshelf/BookshelfDriver.cpp
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)
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@ -299,6 +301,7 @@
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${ispd05_cpps}
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${blif_cpps}
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${spice_cpps}
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${verilog_cpps}
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${lefdef_cpps}
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${openaccess_cpps}
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)
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@ -0,0 +1,37 @@
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Software.
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// Copyright (c) SU/LIP6 2021-2023, All Rights Reserved
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//
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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// | Verilog / Hurricane Interface |
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// | |
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// | Authors : Jean-Paul CHAPUT, Serge Rabyking |
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// | E-mail : Jean-Paul.Chaput@lip6.fr |
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// | =============================================================== |
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// | C++ Header : "./crlcore/Verilog.h" |
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// +-----------------------------------------------------------------+
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#pragma once
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#include <string>
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namespace Hurricane {
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class Cell;
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class Library;
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}
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namespace CRL {
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using Hurricane::Cell;
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using Hurricane::Library;
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class Verilog {
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public:
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static const uint64_t TopCell = (1 << 0);
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public:
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static bool save ( Cell*, uint64_t flags );
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};
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} // CRL namespace.
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@ -3,6 +3,7 @@ crlcore_includes = include_directories(
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'acmsigda',
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'iccad04',
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'spice',
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'verilog',
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'lefdef',
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'blif',
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'alliance/ap',
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@ -85,6 +86,7 @@ crlcore = shared_library(
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'spice/SpiceEntity.cpp',
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'spice/SpiceParser.cpp',
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'spice/SpiceDriver.cpp',
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'verilog/VerilogDriver.cpp',
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'alliance/ap/ApParser.cpp',
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'alliance/ap/ApDriver.cpp',
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'gds/GdsDriver.cpp',
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@ -0,0 +1,371 @@
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Software.
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// Copyright (c) SU 2021-2023, All Rights Reserved
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//
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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// | Verilog / Hurricane Interface |
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// | |
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// | Authors : Jean-Paul CHAPUT, Serge Rabyking |
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// | E-mail : Jean-Paul.Chaput@lip6.fr |
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// | =============================================================== |
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// | C++ Module : "./verilog/VerilogDriver.cpp" |
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// +-----------------------------------------------------------------+
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#include <ctime>
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#include <cmath>
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#include <cstdio>
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#include <cfenv>
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#include <string>
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#include <sstream>
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#include <fstream>
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#include <algorithm>
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#include <unordered_map>
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#include <unordered_set>
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#include <vector>
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#include <set>
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using namespace std;
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#include "hurricane/configuration/Configuration.h"
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#include "hurricane/Warning.h"
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#include "hurricane/DataBase.h"
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#include "hurricane/BasicLayer.h"
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#include "hurricane/Technology.h"
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#include "hurricane/Horizontal.h"
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#include "hurricane/Vertical.h"
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#include "hurricane/Diagonal.h"
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#include "hurricane/Rectilinear.h"
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#include "hurricane/Polygon.h"
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#include "hurricane/Pad.h"
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#include "hurricane/Net.h"
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#include "hurricane/NetExternalComponents.h"
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#include "hurricane/Cell.h"
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#include "hurricane/Plug.h"
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#include "hurricane/Instance.h"
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using namespace Hurricane;
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#include "crlcore/Utilities.h"
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#include "crlcore/NetExtension.h"
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#include "crlcore/ToolBox.h"
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#include "crlcore/Verilog.h"
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//#include "crlcore/VerilogBit.h"
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//#include "crlcore/VerilogEntity.h"
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using namespace CRL;
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namespace CRL {
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static void _write_hdr(ofstream &out)
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{
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time_t clock = time( nullptr );
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tm tm = *localtime( &clock );
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char stamp[1024];
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strftime( stamp, 1024, "%b %d, %Y, %H:%M", &tm );
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out << "/* Coriolis Verilog Driver */" << std::endl;
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out << "/* Generated on " << stamp << " */" << std::endl;
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}
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static void _populate_non_terminal_cells(Cell* cell, std::set<Cell*> &cells)
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{
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if(!cells.insert(cell).second)
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{
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// insertion not happend because it was there already
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return;
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}
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for(Occurrence occurrence: cell->getNonTerminalNetlistInstanceOccurrences())
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{
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Cell* mod = static_cast<Instance*>( occurrence.getEntity() )->getMasterCell();
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// recursively find all related Non-terminal cells (part of the user's design hierarchy)
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_populate_non_terminal_cells(mod, cells);
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}
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}
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std::pair<std::string, int> _wire2bus(std::string name)
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{
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std::pair<std::string, int> bus(name, -1);
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int i = name.size() - 1;
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while (std::isspace(name[i])) --i;// remove trailing spaces just in case
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if(name[i] == ')') // name ends with bracket so is in the form "some_wire_name(index)"
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{
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for(int j = i;;)
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{
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if(--j < 0)
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{
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// didn't find starting bracket
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// this should never happen
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std::cerr << "Wrongly formatted net name: " << name << std::endl;
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assert(false);
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}
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if(name[j] == '(') // find starting bracket
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{
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bus.second = std::stoi(name.substr(j+1, i-j-1)); // get index
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while (std::isspace(name[j-1])) --j; // ignore spaces before starting bracket
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bus.first.erase(j); // trim name to not include index part with brackets
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break;
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}
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}
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}
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return bus;
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}
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static void _write_cell(ofstream &out, Cell* cell)
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{
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out << std::endl;
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std::set<Net*> nets;
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std::vector<Net*> ports, wires;
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for(Instance* instance: cell->getInstances()) // go through all cells instances that form our cell
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{
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for(Plug* plug: instance->getPlugs()) // plugs are connect points of the cells
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{
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Net* net = plug->getMasterNet();
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if(net->isPower() || net->isGround()) // VDD and VSS are not part of Verilog netlist
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{
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continue;
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}
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net = plug->getNet();
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if(net->isExternal()) // propogates through ports
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{
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ports.push_back(net);
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nets.insert(net); // collect all nets we use
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}
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else
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{
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if(!nets.insert(net).second) // the insertion not happend as it was already there
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{
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// this net was already enumerated in some other cell
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// so this wire used at least between two cells and need to be declared
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wires.push_back(net);
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}
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}
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}
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}
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std::map<Net*, std::pair<std::string, int> > net2bus;
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for(Net *net: nets)
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{
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net2bus.insert(std::make_pair(net, _wire2bus(getString(net->getName()))));
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}
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std::vector<std::string> names;
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// collect all port names without indexes in ordered way
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for(Net *net: ports)
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{
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std::string &name = net2bus[net].first;
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auto it = std::lower_bound(names.begin(), names.end(), name);
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if(it == names.end() || (*it) != name) // name not in the list yet
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{
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names.insert(it, name);
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}
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}
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// declare Verilog module with ports names
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out << "module " << getString(cell->getName()) << "(";
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for ( auto it = names.begin(); it != names.end(); ++it)
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{
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out << (*it);
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if (it + 1 != names.end())
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{
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out << ", ";
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}
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}
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out << ");\n";
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// now individually declare each port with direction and width
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for (auto &name: names)
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{
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int idx_min = -1, idx_max;
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Net::Direction dir;
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for (auto it: net2bus)
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{
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if (it.second.first == name) // find net with name
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{
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int idx = it.second.second;
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if (idx < 0)
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{
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if (idx_min >= 0)
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{
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std::cerr << "Net name \"" << name << "\" used with index " << idx_min
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<< " and without index" << std::endl;
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assert(false);
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}
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dir = it.first->getDirection();
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break;
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}
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if (idx_min < 0)
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{
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idx_min = idx_max = idx;
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dir = it.first->getDirection();
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}
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else
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{
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if (idx < idx_min)
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{
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idx_min = idx;
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}
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if (idx > idx_max)
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{
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idx_max = idx;
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}
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if (dir != it.first->getDirection())
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{
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int other = (idx == idx_min)?idx_max:idx_min;
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std::cerr << "Net \"" << name << "\" with index " << idx << " and " << other
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<< " has different directions" << std::endl;
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assert(false);
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}
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}
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}
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}
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if (dir == Net::Direction::IN)
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{
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out << " input ";
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}
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else if (dir == Net::Direction::INOUT)
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{
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out << " inout ";
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}
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else if (dir == Net::Direction::OUT)
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{
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out << " output ";
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}
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else
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{
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std::cerr << "Undetermined direction " << dir << " for the net \"" << name << "\"" << std::endl;
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assert(false);
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}
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if (idx_min >= 0)
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{
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out << "[" << idx_max << ":" << idx_min << "] ";
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}
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out << name << ";" << std::endl;
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}
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// collect all wires (and not ports) names without indexes in ordered way
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names.clear();
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for(Net *net: wires)
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{
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std::string &name = net2bus[net].first;
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auto it = std::lower_bound(names.begin(), names.end(), name);
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if(it == names.end() || (*it) != name) // name not in the list yet
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{
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names.insert(it, name);
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}
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}
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// now individually declare each wire with width
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for (auto &name: names)
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{
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int idx_min = -1, idx_max = -1;
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for (auto it: net2bus)
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{
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if (it.second.first == name) // find all nets by name
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{
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int idx = it.second.second;
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if (idx < 0) // without index
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{
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if (idx_min >= 0)
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{
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std::cerr << "Net name \"" << name << "\" used with index " << idx_min
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<< " and without index" << std::endl;
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assert(false);
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}
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break;
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}
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if (idx_min < 0) // first time encountered
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{
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idx_min = idx_max = idx;
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}
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else
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{
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if (idx < idx_min)
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{
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idx_min = idx;
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}
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if (idx > idx_max)
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{
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idx_max = idx;
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}
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}
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}
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}
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out << " wire ";
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if (idx_min >= 0)
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{
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out << "[" << idx_max << ":" << idx_min << "] ";
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}
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out << name << ";" << std::endl;
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}
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// free not needed resources
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names.clear();
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ports.clear();
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wires.clear();
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nets.clear();
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// declare instancies with connections
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for(Instance* instance: cell->getInstances()) // go through all cells instances that form our cell
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{
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std::vector<Plug*> conns;
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for(Plug* plug: instance->getPlugs()) // plugs are connect points of the cells
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{
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Net* net = plug->getMasterNet();
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if(net->isPower() || net->isGround()) // VDD and VSS are not part of Verilog netlist
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{
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continue;
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}
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// insert in sorted order
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auto it = std::lower_bound(conns.begin(), conns.end(), plug,
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[](Plug* lhs, Plug* rhs) -> bool
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{ return getString(lhs->getMasterNet()->getName()) <
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getString(rhs->getMasterNet()->getName()); });
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conns.insert(it, plug);
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}
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if (conns.empty()) // instance has no connections apart from VSS&VDD
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{
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continue;
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}
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// declare instance
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out << " " << getString(instance->getMasterCell()->getName()) << " "
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<< getString(instance->getName()) << " (" << std::endl;
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// declare connections
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for (auto it = conns.begin(); it != conns.end(); ++it)
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{
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auto &info = net2bus[(*it)->getNet()];
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out << " ." << getString((*it)->getMasterNet()->getName()) << "(" << info.first;
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if (info.second >= 0) // indexed wire
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{
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out << "[" << info.second << "]";
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}
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out << ")";
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if ( it+1 != conns.end()) // not last, so need comma
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{
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out << ",";
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}
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out << std::endl;
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}
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out << " );" << std::endl;
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}
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out << "endmodule" << std::endl;
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}
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// -------------------------------------------------------------------
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// Class : "CRL::Verilog".
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bool Verilog::save ( Cell* cell, uint64_t flags )
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{
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ofstream out(getString(cell->getName()) + ".v");
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_write_hdr(out);
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if (flags & TopCell)
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{
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_write_cell(out, cell);
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}
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else
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{
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std::set<Cell*> cells;
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_populate_non_terminal_cells(cell, cells);
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for (auto &it: cells)
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{
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_write_cell(out, it);
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}
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}
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out.close();
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return true;
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}
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} // CRL namespace.
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@ -56,6 +56,7 @@
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PyAcmSigda.cpp
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#PyIspd05.cpp
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PySpice.cpp
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PyVerilog.cpp
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PyBlif.cpp
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PyGds.cpp
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PyLefImport.cpp
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@ -80,6 +81,7 @@
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crlcore/PyAcmSigda.h
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#crlcore/PyIspd05.h
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crlcore/PySpice.h
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crlcore/PyVerilog.h
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crlcore/PyBlif.h
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crlcore/PyGds.h
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crlcore/PyLefImport.h
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|
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@ -34,6 +34,7 @@
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#include "crlcore/PyAcmSigda.h"
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// #include "crlcore/PyIspd05.h"
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#include "crlcore/PySpice.h"
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#include "crlcore/PyVerilog.h"
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#include "crlcore/PyBlif.h"
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#include "crlcore/PyGds.h"
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#include "crlcore/PyLefImport.h"
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@ -129,6 +130,7 @@ extern "C" {
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PyAcmSigda_LinkPyType ();
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// PyIspd05_LinkPyType ();
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PySpice_LinkPyType ();
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PyVerilog_LinkPyType ();
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PyBlif_LinkPyType ();
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PyGds_LinkPyType ();
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PyLefImport_LinkPyType ();
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@ -154,6 +156,7 @@ extern "C" {
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PYTYPE_READY_NEW ( AcmSigda );
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// PYTYPE_READY_NEW ( Ispd05 );
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PYTYPE_READY_NEW ( Spice );
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PYTYPE_READY_NEW ( Verilog );
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PYTYPE_READY_NEW ( Blif );
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PYTYPE_READY_NEW ( Gds );
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PYTYPE_READY_NEW ( LefImport );
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|
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@ -205,6 +208,8 @@ extern "C" {
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// PyModule_AddObject ( module, "Ispd05", (PyObject*)&PyTypeIspd05 );
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Py_INCREF ( &PyTypeSpice );
|
||||
PyModule_AddObject ( module, "Spice", (PyObject*)&PyTypeSpice );
|
||||
Py_INCREF ( &PyTypeVerilog );
|
||||
PyModule_AddObject ( module, "Verilog", (PyObject*)&PyTypeVerilog );
|
||||
Py_INCREF ( &PyTypeBlif );
|
||||
PyModule_AddObject ( module, "Blif", (PyObject*)&PyTypeBlif );
|
||||
Py_INCREF ( &PyTypeGds );
|
||||
|
|
@ -224,6 +229,7 @@ extern "C" {
|
|||
PyRoutingLayerGauge_postModuleInit ();
|
||||
PyAllianceFramework_postModuleInit ();
|
||||
PySpice_postModuleInit ();
|
||||
PyVerilog_postModuleInit ();
|
||||
PyGds_postModuleInit ();
|
||||
PyDefExport_postModuleInit ();
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,163 @@
|
|||
// -*- C++ -*-
|
||||
//
|
||||
// This file is part of the Coriolis Software.
|
||||
// Copyright (c) SU 2021-2021, All Rights Reserved
|
||||
//
|
||||
// +-----------------------------------------------------------------+
|
||||
// | C O R I O L I S |
|
||||
// | Verilog / Hurricane Interface |
|
||||
// | |
|
||||
// | Authors : Jean-Paul CHAPUT, Serge Rabyking |
|
||||
// | E-mail : Jean-Paul.Chaput@lip6.fr |
|
||||
// | =============================================================== |
|
||||
// | C++ Module : "./PyVerilog.cpp" |
|
||||
// +-----------------------------------------------------------------+
|
||||
|
||||
|
||||
#include "crlcore/PyVerilog.h"
|
||||
#include "hurricane/isobar/PyCell.h"
|
||||
#include "hurricane/isobar/PyLibrary.h"
|
||||
//#include "crlcore/VerilogEntity.h"
|
||||
#include <string>
|
||||
#include <sstream>
|
||||
|
||||
namespace CRL {
|
||||
|
||||
using std::cerr;
|
||||
using std::endl;
|
||||
using std::hex;
|
||||
using std::string;
|
||||
using std::ostringstream;
|
||||
using Hurricane::tab;
|
||||
using Hurricane::Exception;
|
||||
using Hurricane::Bug;
|
||||
using Hurricane::Error;
|
||||
using Hurricane::Warning;
|
||||
using Isobar::ProxyProperty;
|
||||
using Isobar::ProxyError;
|
||||
using Isobar::ConstructorError;
|
||||
using Isobar::HurricaneError;
|
||||
using Isobar::HurricaneWarning;
|
||||
using Isobar::getPyHash;
|
||||
using Isobar::ParseOneArg;
|
||||
using Isobar::ParseTwoArg;
|
||||
using Isobar::__cs;
|
||||
using Isobar::PyCell;
|
||||
using Isobar::PyTypeCell;
|
||||
using Isobar::PyCell_Link;
|
||||
using Isobar::PyLibrary;
|
||||
using Isobar::PyTypeLibrary;
|
||||
using Isobar::PyLibrary_Link;
|
||||
|
||||
extern "C" {
|
||||
|
||||
#if defined(__PYTHON_MODULE__)
|
||||
|
||||
// +=================================================================+
|
||||
// | "PyVerilog" Python Module Code Part |
|
||||
// +=================================================================+
|
||||
|
||||
|
||||
static PyObject* PyVerilog_save ( PyObject*, PyObject* args )
|
||||
{
|
||||
cdebug_log(30,0) << "PyVerilog_save()" << endl;
|
||||
|
||||
HTRY
|
||||
long flags = 0;
|
||||
PyObject* pyCell = NULL;
|
||||
if (PyArg_ParseTuple( args, "Ol:Verilog.save", &pyCell, &flags )) {
|
||||
if (IsPyCell(pyCell)) {
|
||||
Verilog::save( PYCELL_O(pyCell), flags );
|
||||
} else {
|
||||
PyErr_SetString( ConstructorError, "Verilog.save(): Bad parameter type (not a Cell)." );
|
||||
return NULL;
|
||||
}
|
||||
} else {
|
||||
std::cout << ConstructorError << std::endl;
|
||||
PyErr_SetString( ConstructorError, "Verilog.save(): Bad number of parameters." );
|
||||
return NULL;
|
||||
}
|
||||
HCATCH
|
||||
|
||||
Py_RETURN_NONE;
|
||||
}
|
||||
|
||||
|
||||
// static PyObject* PyVerilog_load ( PyObject*, PyObject* args )
|
||||
// {
|
||||
// cdebug_log(30,0) << "PyVerilog_load()" << endl;
|
||||
|
||||
|
||||
// HTRY
|
||||
// unsigned long mode = 0;
|
||||
// char* path = NULL;
|
||||
// PyObject* pyLibrary = NULL;
|
||||
// if (PyArg_ParseTuple( args, "Osk:Verilog.load", &pyLibrary, &path, &mode )) {
|
||||
// if (IsPyLibrary(pyLibrary)) {
|
||||
// Verilog::load( PYLIBRARY_O(pyLibrary), string(path), (uint64_t)mode );
|
||||
// } else {
|
||||
// PyErr_SetString( ConstructorError, "Verilog.load(): Bad parameter type (not a Library)." );
|
||||
// return NULL;
|
||||
// }
|
||||
// } else {
|
||||
// PyErr_SetString( ConstructorError, "Verilog.load(): Bad number of parameters." );
|
||||
// return NULL;
|
||||
// }
|
||||
// HCATCH
|
||||
|
||||
// Py_RETURN_NONE;
|
||||
// }
|
||||
|
||||
|
||||
// static PyObject* PyVerilog_clearProperties ( PyObject* )
|
||||
// {
|
||||
// cdebug_log(30,0) << "PyVerilog_clearProperties()" << endl;
|
||||
// HTRY
|
||||
// Verilog::clearProperties();
|
||||
// HCATCH
|
||||
// Py_RETURN_NONE;
|
||||
// }
|
||||
|
||||
|
||||
// Standart Destroy (Attribute).
|
||||
|
||||
|
||||
PyMethodDef PyVerilog_Methods[] =
|
||||
{ { "save" , (PyCFunction)PyVerilog_save , METH_VARARGS|METH_STATIC
|
||||
, "Save a complete Verilog design." }
|
||||
// , { "load" , (PyCFunction)PyVerilog_load , METH_VARARGS|METH_STATIC
|
||||
// , "Load a Verilog layout inside a Cell (cumulative)." }
|
||||
// , { "clearProperties" , (PyCFunction)PyVerilog_clearProperties, METH_NOARGS|METH_STATIC
|
||||
// , "Remove all Verilog related properties from the Cells." }
|
||||
, {NULL, NULL, 0, NULL} /* sentinel */
|
||||
};
|
||||
|
||||
|
||||
NoObjectDeleteMethod(Verilog)
|
||||
PyTypeObjectLinkPyTypeWithoutObject(Verilog,Verilog)
|
||||
|
||||
|
||||
#else // End of Python Module Code Part.
|
||||
|
||||
|
||||
// +=================================================================+
|
||||
// | "PyVerilog" Shared Library Code Part |
|
||||
// +=================================================================+
|
||||
|
||||
// Type Definition.
|
||||
PyTypeObjectDefinitionsOfModule(CRL,Verilog)
|
||||
|
||||
|
||||
extern void PyVerilog_postModuleInit ()
|
||||
{
|
||||
PyObject* constant;
|
||||
|
||||
LoadObjectConstant(PyTypeVerilog.tp_dict,::CRL::Verilog::TopCell ,"TopCell");
|
||||
}
|
||||
|
||||
|
||||
#endif // End of Shared Library Code Part.
|
||||
|
||||
} // extern "C".
|
||||
|
||||
} // CRL namespace.
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
// -*- C++ -*-
|
||||
//
|
||||
// This file is part of the Coriolis Software.
|
||||
// Copyright (c) SU 2021-2023, All Rights Reserved
|
||||
//
|
||||
// +-----------------------------------------------------------------+
|
||||
// | C O R I O L I S |
|
||||
// | Verilog / Hurricane Interface |
|
||||
// | |
|
||||
// | Authors : Jean-Paul CHAPUT, Serge Rabyking |
|
||||
// | E-mail : Jean-Paul.Chaput@lip6.fr |
|
||||
// | =============================================================== |
|
||||
// | C++ Header : "./crlcore/PyVerilog.h" |
|
||||
// +-----------------------------------------------------------------+
|
||||
|
||||
|
||||
#pragma once
|
||||
#include "hurricane/isobar/PyHurricane.h"
|
||||
#include "crlcore/Verilog.h"
|
||||
|
||||
|
||||
namespace CRL {
|
||||
|
||||
extern "C" {
|
||||
|
||||
|
||||
// -------------------------------------------------------------------
|
||||
// Python Object : "PyVerilog".
|
||||
|
||||
typedef struct {
|
||||
PyObject_HEAD
|
||||
} PyVerilog;
|
||||
|
||||
|
||||
// -------------------------------------------------------------------
|
||||
// Functions & Types exported to "PyCRL.ccp".
|
||||
|
||||
extern PyTypeObject PyTypeVerilog;
|
||||
extern PyMethodDef PyVerilog_Methods[];
|
||||
|
||||
extern void PyVerilog_LinkPyType ();
|
||||
extern void PyVerilog_postModuleInit ();
|
||||
|
||||
#define IsPyVerilog(v) ( (v)->ob_type == &PyTypeVerilog )
|
||||
#define PY_VERILOG(v) ( (PyVerilog*)(v) )
|
||||
|
||||
} // extern "C".
|
||||
|
||||
} // Hurricane namespace.
|
||||
|
|
@ -18,6 +18,7 @@ pyCRL_files = files([
|
|||
'PyGraphicToolEngine.cpp',
|
||||
'PyAcmSigda.cpp',
|
||||
'PySpice.cpp',
|
||||
'PyVerilog.cpp',
|
||||
'PyBlif.cpp',
|
||||
'PyGds.cpp',
|
||||
'PyLefImport.cpp',
|
||||
|
|
|
|||
Loading…
Reference in New Issue