* Bug: In CRL::BlifParser::Model CTOR, forgot to set the direction
on auto-generated power supply global nets. So they were put
in "linkage" in the VST files.
* New: In CRL::DefImport, add specific support for the Sky130/Caravel
harness "user_project_wrapper".Mainly:
- Do not fuse together "io_in" and "io_out" as a single net as
they should (according to the DEF). So we can connect separately
on each of them. We only allow one port for each net, as in VHDL.
* Bug: In CRL::MeasureSet::toStringHeaders(), check and issue a warning
if a measure label ends with a "." (dot).
* Change: In CRL::ToolEngine::getMeasure(), return the data measure
by pointer instead of by reference (easier to manipulate afterwards).
* New: In EtesianEngine::place(), add the placement runtime (under label
"placeT") to the measure set.
* New: In KatanaEngine::dumpMeasures(), add the Etesian runtime to the
set of measures.
WARNING: We are partially duplicating the informations pertaining
to the Alliance catalog (stored in the Catalog property)
directly into the Cell. This is needed for Flexlib which
is not using the Alliance loading mechanim. Ideally the
Catalog information should be moved into the Cell.
* New: In Cell, add new state flags Diode, PowerFeed (in addition to
Pad & Feed).
Export flags setter/getter to Python. For Flexlib usage.
* Change: In AllianceFramework::getInstancesCount(), correctly skip
Diode & Feeds based on Cell flags. Those flags must correctly
be set in the various Flexlib_fix.py scripts.
* New: In AllianceFramework::getInstancesCount(), add a flag TerminalNetlist
to stop recursion on "terminal for netlist" instance level. This is to
avoid counting physical only or non-routed instances inside hard macros,
like SRAM blocks. This was leading to an overstimation of the "size"
in number of gates of the routing problem.
* Change: In KatanaEngine CTOR, call for the terminal for netlist number of
gates...
* Bug: In all CMakeLists.txt, it seems I was doing a worng use of
target_link_library(). No longer add dependencies to the C++ base
library but instead either to the Python associated module or
to the final binaries. This was inderectly causing the linking
problem related to Python (which was a misdirection).
* Bug: Typo in FindLibexecinfo.cmake, do not use FindLib[E]xecinfo.
* Change: In CRL/ccore/CMakeLists.txt, activate SKIP_AUTOMOC on
bison/flex generated files.
* Bug: In viewer/PyHApplication, do not delete the C++ object in
the Python destroy method.
* New: In CRL::DefImport, the previous version of the parser was designed
only to read pure netlists, no physical components. Now add features
for:
* VIA generate statements. Generated VIAs are created as Cell and
then instaciated wherever they are needed. Alternative would be
to duplicate it's contents so the original netlist is not changed.
But would create lot more objects.
* PIN, added support for basic physical shapes.
* SPECIALNETS and their associated wiring (path callback).
Note: (to myself) As the Path is created *before* the NET or SPECIALNET
callback is called, we must create a temporary net to store
the path components. This is the "__prebuild__" net which
will be merged later with the actual net.
* Bug: In CRL::GdsDriver::GdsStream::operator<<(Cell*), when looking for
layer names ending with ".pin", must also check that the string is
at least 4 characters long.
Note: We don't suppress warnings due to unused variables or functions,
as we may need them later or in debug mode...
* Change: In Hurricane::DBo::~DBo, add a noexcept(false) because
constructed by default destructor of derived classes seems to
loosen it. The right solution whould be to explicitely define
all virtual destructors (too lazy for now).
* Change: In Viewer::Script, replace the deprecated
PyModule_GetFilename() by PyModule_GetFilenameObject(), Unicode
support again...
* New: Python/C++ API level:
* Write a new C++/template wrapper to get rid of boost::python
* The int & long Python type are now merged. So a C/C++ level,
it became "PyLong_X" (remove "PyInt_X") and at Python code
level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
* Configuration is now integrated as a Hurricane component,
makes use of the new C++/template wrapper.
* vlsisapd is now defunct. Keep it in the source for now as
some remaining non essential code may have to be ported in
the future.
* Note: Python code (copy of the migration howto):
* New print function syntax print().
* Changed "dict.has_key(k)" for "k" in dict.
* Changed "except Exception, e" for "except Exception as e".
* The division "/" is now the floating point division, even if
both operand are integers. So 3/2 now gives 1.5 and no longer 1.
The integer division is now "//" : 1 = 3//2. So have to carefully
review the code to update. Most of the time we want to use "//".
We must never change to float for long that, in fact, represents
DbU (exposed as Python int type).
* execfile() must be replaced by exec(open("file").read()).
* iter().__next__() becomes iter(x).__next__().
* __getslice__() has been removed, integrated to __getitem__().
* The formating used for str(type(o)) has changed, so In Stratus,
have to update them ("<class 'MyClass'>" instead of "MyClass").
* the "types" module no longer supply values for default types
like str (types.StringType) or list (types.StringType).
Must use "isinstance()" where they were occuring.
* Remove the 'L' to indicate "long integer" (like "12L"), now
all Python integer are long.
* Change in bootstrap:
* Ported Coriolis builder (ccb) to Python3.
* Ported Coriolis socInstaller.py to Python3.
* Note: In PyQt4+Python3, QVariant no longer exists. Use None or
directly convert using the python syntax: bool(x), int(x), ...
By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
* In order to compile user's must upgrade to my own rebuild of
PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
buffer of the H-Tree to the original signal (mainly: top clock).
Strangely, it was only done when working in full chip mode.
SPICE simulators don't like to have the same model defined twice.
As we have a "one file per model policy", then we must include the
model file only once. This is particularly critical for standard
cells. So now, the driver include all the models in the top level,
both terminals ans intermediate. And the sub-models include nothing.
We stop at the "TerminalNetlist" level.
Add an option flag througout all the Spice driver hierarchy to
convey that information.
The structure of the driver is copied from the Vhdl one. It is not
integrated as a an AllianceFramework one but as a standalone like
GDS. For now use numerical indexes for electrical nodes but also
support strings. The nets are ordereds in reverse alphabetical
order, but a custom order can be defined, if we read the model
from an external SPICE subckt (to be done).
SPICE saving has also been added to the cumulus/rsave plugin
and the block/chip P&R one.
* Change: In GdsStream::_gdsLayerTable, use a map<> instead of a vector<>,
use a combined value of the layer index and the datatype as index.
(index = (layer<<16) + datatype.
This allow for layers that are represented by a pair of (layer,datatype)
with same layer and different datatypes.
* Change: In GdsStream::gdsToLayer(), now have two parameters, the layer
and the datatype.
* Bug: In CRL::GdsParser(), the table of GDS layer was limited to 64,
which is the maximum, according to the reference. But it is no
longer true. Extend to 256.
This was leading to GDS files missing some layers.
* New: In CRL::GdsStream::xyToPath(), now manage BGNEXTN & ENDEXTN for
PATHTYPE 4.
The begin/end Contact are created to use exactly the area of the
extension. Otherwise there were overspill when the size of the
extension is greater than the width of the path. Also need to do
a sligth shift if the extension is an odd number of foundry grid.
This fix the offgrid problems.
* New: In CRL::PyCatalog, add the second parameter "add" to getState()
so we can request the creation of the state if needed.
* New: In CRL::PyCatalogState, export setCell() and setInMemory() methods.
* Bug: In CRL::Subckt::createModel(), when a cell has a State entry in
the catalog, also check that it really has a Cell loaded in memory.
If not, throw an exception (and do not crash).
* New: In CRM::GdsSteam::makeExternals(), now take into accounts Pad
for Net external components. Also delete the original components
after creating the copy in the right Net.
So now the PLL terminals are correctly seen.
* Bug: In CRL::GdsParser, the PLL was using copies of the standard cell
with the same name. And unfortunately, they where found *before*
the FlexLib one when using DataBase::getCell(). As their I/O where
wrong it was leading to a massive netlist connexion corruption in
blif2vst.
To avoid that, any Cell created by the GDS parser is now prefixed
by "gds_".
* Change: In CRL::GdsStream CTOR, report when the file cannot be opened
instead of saying that the GDS file is corrupted (misleading).
* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
are part of a vector, but *not* in the "downto" direction,
unvectorize anyway. In the component declarations, vectors are
always in "downto" order, so they must also be mapped in that
order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
signal names different from instance names for VHDL compliance.
This is complementary to what is done in blif2vst.
No completely satisfied with that. Should find a more generic
way to do it in the future.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
the external status of the former Net. When a Net::merge() is
performed, we must keep track of whether the merged (destroyed)
one was external and keep that information.
Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
search of the net name in *internal* aliases. Otherwise only the
aliases tagged as *external* will be searched.
It was a bug that, when looking for a Plug master net by name
we got an homonymous internal net. In that case we must only
look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
unvectorize it, like when it is non-contiguous (we use the
isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
a flag UniquifyUpperCase to uniquify the names in uppercases.
In case of a clash with the same name in lowercase.
Prepend 'u' before all previously uppercased letter. For
example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
The Catalog flags is exported to Python for use by the blif2vst
script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
a new gate each time it is called instead of making just one for
each Model. This way, if two outside nets are connected to one
or zero they do not get merged (should work, but will be less
clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
master net in the instances models (by name), limit the search
to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
(i.e. components) with 'cmpt_' to avoid clash names with signals
in VHDL.
* Change: In CRL::GdsStream::operator<<(Cell*), external components needs
to be exported twice. First as "METALx.pin" to signal an external
component (and give it's name). And second as a "normal" component
in "METALx". If the METALx part is forgotten, the "Vendor" StreamIn
will not see the METALx.pin as something physical so f***g gaps appears
in the wiring. And furthermore, if the TEXT label is above it, the
name of the net goes away...
* New: CRL::SubNetNames (in ToolBox), takes a VHDL signal name, vectorized
or not and allow to generated sub-net names from it, with respect to
the original vector name.
Examples:
* machin -> machin_hfns_0, machin_hfns_1, ...
* bidule(3) -> bidule_bit3_hfns_0, bidule_bit3_hfns_1, ...
Makes use of the POSIX regex library to avoid Boost dependencies.
* New: CRL::restoreNetsdirection() (in ToolBox) that checks the coherency
of all Nets direction through a complete hierarchy of cells.
Stops at Cells flagged "TerminalNetlist".
Directions are rebuilt for all the Cells part of the hierarchy
in a bottom up fashion. It is also checked that Nets have only one
driver (we assume there is no three-state busses).
To sort cells in hierarchical order (bottom up according to their
depth), copy the DepthOrder class from the GDSII driver. Will unify
them later.
exported to the Python interface.
* New: In cumulus/tools/blif2vst.py, add a call to restoreNetsdirection()
before saving.
gatecat
Jean-Paul Chaput
Myrtle Shah
Luke Kenneth Casson Leighton