* Change: In <tool>/CMakeLists.txt, add an USE_LIBBFD option to
enable the link against the BFD library. Latest versions seems
to have changed their API.
* Change: In bootstrap/ccp.by & builder/Builder.py, add an option
"--bfd" (and self._bfd) to enable BFD support.
In the LS180, probably due to the implementation of a small RAM
with DFFs, some leaf of the clock tree (H-Tree) got heavily
loaded (around 80 DFFs sinks). Implement an option that allow
the leaf of the QuadTree to use three buffers instead of one.
The sinks are partitionned using their angle from the center
of the leaf (trigonometric direction). CChoose the bigger angle
gaps to perform the split.
* Change: In Cumulus/plugins.block.configuration.GaugeConf, in
getNearestHorizontalTrack() and getNearestVerticalTrack() add an
offset argument to shift the position of the requested track
by a certain amount.
* Change: In Cumulus/plugins.block.configuration.GaugeConf, in
createHorizontal(), add a flag to make the source end of the
segment to "stick out". Useful when connecting to a stacked
VIA top, but using a lower layer that can be shifted.
* New: In Cumulus/plugins.block.spares.Spares, BufferPool & QuadTree,
add support for selection and management of multiple buffers at
the same time. Basically returns a list of selected buffer
instances instead of just one instance.
Added HEAVY_LEAF_LOAD flag to Spares. To be used by all tools
classes that makes use of it.
Added QuadTree.runselect(), be sure to call it between different
H-Tree operations, otherwise results will be strange.
* New: In Cumulus/plugins.block.htree.HTree, in case of heavy leaf
load, in the leaf of the tree, allocate three buffers instead
of one. Select them to form a triangle around the main one.
That is, use (i,j), (i+1,j) and (i,j+1).
Added a HTree._connectLeaf() to share the handling of the child
buffer connexions. Whether they are leaf of not and heavy or not.
* Change: Cumulus/plugins.block.Block, expand HTree support to
manage the HEAVY_LEAF_LOAD flag.
* Bug: In CRL/etc/symbolic/plugins.py, power lines around the core where
badly spaced, allowing the filler to insert a fill wire that was
causing both DRC error and short circuit.
* In Cumulus/plugins/block/macro.py, the METAL3 blokage was too narrow
on the left side, allowing use of METAL3 track too close from
internal components.
The METAL5 blockages around jumpers where also too narrow.
Thoses problems where seen with the density filler which put
wires everywhere.
* Bug: In Track::repair(), consider the blockage net as any other, so
the metal filling works correctly (correct management of transitions
between blockage and non-blockage).
* Change: In Etesian::Slice::fillHole(), instead of cramming the home
with tix_x0 only, put one tie at both ends and fill the rest
with fill_x0. This should help the vendor density filler to
equalze.
* New: In Etesian::Configuration, add the parameter:
"etesian.tieName" (for tix_x0) as it now separate from the simple
filler cells.
* In Etesian::BloatFlexLib::getDx(), expand the "mx2_x2" of one more
pitch (2 instead of 1). The P&R was unable to allocate a critical
diode under a slice that was littered with those cells in LS180.
SPICE simulators don't like to have the same model defined twice.
As we have a "one file per model policy", then we must include the
model file only once. This is particularly critical for standard
cells. So now, the driver include all the models in the top level,
both terminals ans intermediate. And the sub-models include nothing.
We stop at the "TerminalNetlist" level.
Add an option flag througout all the Spice driver hierarchy to
convey that information.
* Bug: In cumulus/plugins.chip.libresocio, the ioPadInfos where inverting
"d" and "s" terminals on IOPadInOut. This was indirectly detected by
the DRC complaining about floating gates on the "d" connected nets!
* New: cumulus/plugins.checks, plugin providing a oneDriver() function
to check that each net has one and only one driver. This is for
Cell that are not P&R (in which it is also checked). So, typically
the chip level.
* New: In cumulus/plugins.chip.core2chip, add a call to oneDriver().
* Bug: In cumulus/plugins.chip.core2chip, clear Spice extensions after
save. Otherwise we may use an outdated Spice extension after the
P&R. This is were Net missing Spice::Bit may occur.
The structure of the driver is copied from the Vhdl one. It is not
integrated as a an AllianceFramework one but as a standalone like
GDS. For now use numerical indexes for electrical nodes but also
support strings. The nets are ordereds in reverse alphabetical
order, but a custom order can be defined, if we read the model
from an external SPICE subckt (to be done).
SPICE saving has also been added to the cumulus/rsave plugin
and the block/chip P&R one.
Protections diodes may not be able to play their role if they are
separated from their cluster by upper level layers (METAL4/METAL5).
This seems not to diminish the total number of diodes.
* New: In Anabatic::NetData, add a set of non move up segments in
the object. To tag global wires that are part of a cluster.
* New: In Anabatic::AutoSegment, add support for a SegNoMoveUp
flag. This flag is propagated through _makeDogleg() .
Used in ::canMoveUp() and ::canPivotUp().
* New: In Anabatic::NetBuilder, add NetData to the attributes so
we can extract the NoMoveUp infomation given by the antenna
protect stage.
* New: In NetBuilderHV::_do_globalSegment(), lookup NoMoveUp
information from NetData to put it in AutoSegment.
* New: In AntennaProtect(Net*), flags the RoutingPad clusters wires
as non movable up.
* New: In AnabaticEngine::breatAt(GCell*), propagate the SegNoMoveUp
flags. Based on NetData.
* Bug: In AutoSegment::canReduce(), in the repair stage, segments are
allowed to go beyond their GCell bondaries, so global segments can
end up in zero length. So now allow globals less than one P-Pitch
to be flagged as reduced.
* Bug: In AutoSegment::isMiddleStack(), systematically reject non-canonical
segment. If it is non-canonical, then is aligned with a canonical one.
Then we will perform the check on it.
There seems to be another porblem of update of the length of the
associated TrackElement, the increase of size of the non-canonical is
not taken into account. This is enough to prevent the problem to
arise but we should invsetigate further.
* Hack: In AutoSegment::canMoveUp(), prevent segment id:6378409 to be
moved up so the last antenna effect is avoided. This is not a clean
way to do it.
* Change: In GdsStream::_gdsLayerTable, use a map<> instead of a vector<>,
use a combined value of the layer index and the datatype as index.
(index = (layer<<16) + datatype.
This allow for layers that are represented by a pair of (layer,datatype)
with same layer and different datatypes.
* Change: In GdsStream::gdsToLayer(), now have two parameters, the layer
and the datatype.
* Change: In Katana::PowerRails, in TerminalNetlist cells instances,
the ordinary nets components where generating obstacles, leading
to stupid cross blockages between the obstacle generated by the
component supporting the routing pad and the RP itself.
Now only take into account supplies and clocks (any layers)
and blockage layers.
Fix symbolic benches.
* Change: In Katana::Manipulator::moveUp(), the "reserve" value was
of 0.5 for pivot up and locals, now set it to 1.0, like in all
other cases ("reserve" is the number of free tracks that is
needed to allow the move up, in addition the the length being
moved up).
Fix routing convergence on the MIPS pipeline bench.
* Bug: In CRL::GdsParser(), the table of GDS layer was limited to 64,
which is the maximum, according to the reference. But it is no
longer true. Extend to 256.
This was leading to GDS files missing some layers.
* Bug: In TrackSegment::isMiddleStack(), formerly, all global segments
where discarted. But in the routing repair stage, segments can go
*outside* their GCell boundaries, allowing globals to became of
null length.
Hence, for global, we now also check the wirelength.
* Change: In cumulus/plugins.chip.chip.doConnectCore(), do not use the
feature of the HTree to connect the root buffer straight to the
corona pin. It prevents the router to insert a diode when those
wires are too long. So let the standard router manage them.
Should add diode insertions in HTree.connectHTrees() later.
* Bug: In Track::repair(), when a same net gap has been found and closed,
we display a warning. We display the two segments fused, but when it's
the two first, we must not use index "i-1" (with i=0) ...
* Bug: In cumulus/plugins.chip.powerplane.Builder._connectHTree(),
when building the stacked VIAs over the corona Pin and the
root buffer RoutingPad, pass the GaugeConf.HAccess flag so the
stack stops at METAL4 (top horizontal layer).
Before we where also adding a VIA up to METAL5 which was unused
and caused a minimal area violation.
* Change: In AutoSegment::isMiddleStack(), after checking for obvious
non-candidates, relies on axis-to-axis wirelength instead of topological
criterions. We will not be able to account all the topologies that
may cause problem. So consider every segment whose length is below
one perpandicular pitch.
* Change: In cumulus/plugins.block.macro, the METAL2 blockage was
allowing horizontal tracks to be used but the METAL3 blockage
was conflicting with the end of the perpandiculars.
The router was not able to manage that, so we slightly expand
the METAL2 blockage to encompass the unreachable track.
For the same reason, add a METAL4 blockage over METAL2.
* New: In cumulus/plugins.chip.pads, add METAL5 jumpers on all wires
going to/from the I/O pads on the East & West side. This is a
quick hack as:
1. We should put it also on North/South, but no violation
happens here.
2. We should put it on *ouput* wire only (for only those are
connected to transistors gates).
* New: In cumulus/plugins.chip.macro, put jumpers on the East side
connectors for the SRAM block. Also a quick hack, not robust for
anything else than the SRAM.
Las Safin
Jean-Paul Chaput
Luke Kenneth Casson Leighton