* New: Python/C++ API level:
* Write a new C++/template wrapper to get rid of boost::python
* The int & long Python type are now merged. So a C/C++ level,
it became "PyLong_X" (remove "PyInt_X") and at Python code
level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
* Configuration is now integrated as a Hurricane component,
makes use of the new C++/template wrapper.
* vlsisapd is now defunct. Keep it in the source for now as
some remaining non essential code may have to be ported in
the future.
* Note: Python code (copy of the migration howto):
* New print function syntax print().
* Changed "dict.has_key(k)" for "k" in dict.
* Changed "except Exception, e" for "except Exception as e".
* The division "/" is now the floating point division, even if
both operand are integers. So 3/2 now gives 1.5 and no longer 1.
The integer division is now "//" : 1 = 3//2. So have to carefully
review the code to update. Most of the time we want to use "//".
We must never change to float for long that, in fact, represents
DbU (exposed as Python int type).
* execfile() must be replaced by exec(open("file").read()).
* iter().__next__() becomes iter(x).__next__().
* __getslice__() has been removed, integrated to __getitem__().
* The formating used for str(type(o)) has changed, so In Stratus,
have to update them ("<class 'MyClass'>" instead of "MyClass").
* the "types" module no longer supply values for default types
like str (types.StringType) or list (types.StringType).
Must use "isinstance()" where they were occuring.
* Remove the 'L' to indicate "long integer" (like "12L"), now
all Python integer are long.
* Change in bootstrap:
* Ported Coriolis builder (ccb) to Python3.
* Ported Coriolis socInstaller.py to Python3.
* Note: In PyQt4+Python3, QVariant no longer exists. Use None or
directly convert using the python syntax: bool(x), int(x), ...
By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
* In order to compile user's must upgrade to my own rebuild of
PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
buffer of the H-Tree to the original signal (mainly: top clock).
Strangely, it was only done when working in full chip mode.
* Change: In <tool>/CMakeLists.txt, add an USE_LIBBFD option to
enable the link against the BFD library. Latest versions seems
to have changed their API.
* Change: In bootstrap/ccp.by & builder/Builder.py, add an option
"--bfd" (and self._bfd) to enable BFD support.
* Bug: In CRL/etc/symbolic/plugins.py, power lines around the core where
badly spaced, allowing the filler to insert a fill wire that was
causing both DRC error and short circuit.
SPICE simulators don't like to have the same model defined twice.
As we have a "one file per model policy", then we must include the
model file only once. This is particularly critical for standard
cells. So now, the driver include all the models in the top level,
both terminals ans intermediate. And the sub-models include nothing.
We stop at the "TerminalNetlist" level.
Add an option flag througout all the Spice driver hierarchy to
convey that information.
The structure of the driver is copied from the Vhdl one. It is not
integrated as a an AllianceFramework one but as a standalone like
GDS. For now use numerical indexes for electrical nodes but also
support strings. The nets are ordereds in reverse alphabetical
order, but a custom order can be defined, if we read the model
from an external SPICE subckt (to be done).
SPICE saving has also been added to the cumulus/rsave plugin
and the block/chip P&R one.
* Change: In GdsStream::_gdsLayerTable, use a map<> instead of a vector<>,
use a combined value of the layer index and the datatype as index.
(index = (layer<<16) + datatype.
This allow for layers that are represented by a pair of (layer,datatype)
with same layer and different datatypes.
* Change: In GdsStream::gdsToLayer(), now have two parameters, the layer
and the datatype.
* Bug: In CRL::GdsParser(), the table of GDS layer was limited to 64,
which is the maximum, according to the reference. But it is no
longer true. Extend to 256.
This was leading to GDS files missing some layers.
* New: In CRL::GdsStream::xyToPath(), now manage BGNEXTN & ENDEXTN for
PATHTYPE 4.
The begin/end Contact are created to use exactly the area of the
extension. Otherwise there were overspill when the size of the
extension is greater than the width of the path. Also need to do
a sligth shift if the extension is an odd number of foundry grid.
This fix the offgrid problems.
* New: In CRL::PyCatalog, add the second parameter "add" to getState()
so we can request the creation of the state if needed.
* New: In CRL::PyCatalogState, export setCell() and setInMemory() methods.
* Bug: In CRL::Subckt::createModel(), when a cell has a State entry in
the catalog, also check that it really has a Cell loaded in memory.
If not, throw an exception (and do not crash).
* New: In CRM::GdsSteam::makeExternals(), now take into accounts Pad
for Net external components. Also delete the original components
after creating the copy in the right Net.
So now the PLL terminals are correctly seen.
* Bug: In CRL::GdsParser, the PLL was using copies of the standard cell
with the same name. And unfortunately, they where found *before*
the FlexLib one when using DataBase::getCell(). As their I/O where
wrong it was leading to a massive netlist connexion corruption in
blif2vst.
To avoid that, any Cell created by the GDS parser is now prefixed
by "gds_".
* Change: In CRL::GdsStream CTOR, report when the file cannot be opened
instead of saying that the GDS file is corrupted (misleading).
* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
are part of a vector, but *not* in the "downto" direction,
unvectorize anyway. In the component declarations, vectors are
always in "downto" order, so they must also be mapped in that
order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
signal names different from instance names for VHDL compliance.
This is complementary to what is done in blif2vst.
No completely satisfied with that. Should find a more generic
way to do it in the future.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
the external status of the former Net. When a Net::merge() is
performed, we must keep track of whether the merged (destroyed)
one was external and keep that information.
Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
search of the net name in *internal* aliases. Otherwise only the
aliases tagged as *external* will be searched.
It was a bug that, when looking for a Plug master net by name
we got an homonymous internal net. In that case we must only
look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
unvectorize it, like when it is non-contiguous (we use the
isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
a flag UniquifyUpperCase to uniquify the names in uppercases.
In case of a clash with the same name in lowercase.
Prepend 'u' before all previously uppercased letter. For
example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
The Catalog flags is exported to Python for use by the blif2vst
script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
a new gate each time it is called instead of making just one for
each Model. This way, if two outside nets are connected to one
or zero they do not get merged (should work, but will be less
clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
master net in the instances models (by name), limit the search
to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
(i.e. components) with 'cmpt_' to avoid clash names with signals
in VHDL.
* Change: In CRL::GdsStream::operator<<(Cell*), external components needs
to be exported twice. First as "METALx.pin" to signal an external
component (and give it's name). And second as a "normal" component
in "METALx". If the METALx part is forgotten, the "Vendor" StreamIn
will not see the METALx.pin as something physical so f***g gaps appears
in the wiring. And furthermore, if the TEXT label is above it, the
name of the net goes away...
* New: CRL::SubNetNames (in ToolBox), takes a VHDL signal name, vectorized
or not and allow to generated sub-net names from it, with respect to
the original vector name.
Examples:
* machin -> machin_hfns_0, machin_hfns_1, ...
* bidule(3) -> bidule_bit3_hfns_0, bidule_bit3_hfns_1, ...
Makes use of the POSIX regex library to avoid Boost dependencies.
* New: CRL::restoreNetsdirection() (in ToolBox) that checks the coherency
of all Nets direction through a complete hierarchy of cells.
Stops at Cells flagged "TerminalNetlist".
Directions are rebuilt for all the Cells part of the hierarchy
in a bottom up fashion. It is also checked that Nets have only one
driver (we assume there is no three-state busses).
To sort cells in hierarchical order (bottom up according to their
depth), copy the DepthOrder class from the GDSII driver. Will unify
them later.
exported to the Python interface.
* New: In cumulus/tools/blif2vst.py, add a call to restoreNetsdirection()
before saving.
* New: In CRL::RoutingLayerGauge, add a new kind of gauge "PowerSupply"
to flag a layer which is dedicated to routing power supplies.
* New: In AllianceFramework, add management of PowerSupply gauge kind.
Exported in the Python interface.
* Change: In Model::connectSubckts(), when trying to lookup the
Hurricane Net from it's Blif name, try first as a VHDL one then
after a Verilog to VHDL translation. Especially useful for bits
of vectorized names ("signal[X]" --> "signal(X)").
The policy about how to create slots was not completly clear.
Now, only add *pointers* or *references* to class attributes,
never do a "copy by value". Reflect that change in SlotTemplate<>
various partial specializations.
Hammer in your head that in C++ functions templates do not allow
for partial specialization. So write only *one* template for
::getSlot<>() (refdefinition simply got ignoreds, at least with gcc).
* Bug: In Slot, only one template for getSlot<> (see above).
Adjust SlotTemplates<> to provides partial specialization only for:
* "const Data&".
* "Data*".
* "const Data*".
* "Data* const"
* "Record*".
* Bug: In Instance::_getRecord(), suppress slot based on transient
values "XCenter" & "YCenter".
* Bug: In CRL::ToolEngine::_getRecord(), suppress slot "Name" based
on a transient value.
* Change: In ::getRecord(std::list<Elementt>*) (and variant), pass
all elements to ::getSlot() as (const Element*).
* In CRL::GdsStream::operator<<(Cell*), when encountering an *external*
component, try to find a ".pin" layer associated (if not already
in it). Then drive the BOUNDARY & TEXT in it. This way, Cadence/
Calibre seems to be able to recognize them as Pin.
* New: In CRL::GdsDriver, create TEXT record under each external
Net component. Seems to be the aknoweledged way to signal
external pins.
* New: In CRL::GdsParser, read TEXT record and create Net and
external components that are in the same layer and at the
same position.
* New: In CRL/hepers, new function onFGrid() to ensure a DbU is on the
foundry grid. Rounding is always done to the inferior integer.
* New: In CRL/GdsDriver, added a set of isOnGrid() functions to check
that all coordinates of various objects are on the foundry grid.
Use isOnGrid() in most objects processed in
GdsStream::operator<<(Cell*).
* Bug: In cumulus/plugins.chip.pads.Corner, correctly round the
coordinates of the 45 degree segments so they are still on the
foundry grid.
* New: In cumulus/plugins.core2chip.libresocio.CoreToChip, use new
configuration variable "chip.useAbstractpads" to select between the
abstract version (GPIO, VDD, ...) and the full version (IOPadInOut,
IOPadVdd, ...) layout.
* Change: In CRL::Model::staticInit(), when trying to guess the ouput
of the tie low & tie high cells check if the net name is not a
power or ground. A bad input was choosen with FlexLib as the
vdd/vss nets where not typed as POWER/GROUND.
* Change: In Hurricane::QuadTree_GosUnder::Locator::progress(), directly
prune the elements which sizes are under the threshold. This allows
the too small Instances to be directly skipped. This was the key
point slowing the walktrough. We were systematically going through
all the instances (that is consistent with the perf traces).
* Change: In Hurricane::Cell_OccurrencesUnder, add a threshold parameter
to pass on the QuadTree (through getInstancesUnder()).
Needed for the CellWidget selection to have the same problem as
the display itself (select only what is displayed).
* New: In Hurricane::CellView, add two new parameters:
1. "viewer.minimumSize" set the original size of the window, in pixels.
(doubled for HiDPI).
2. "viewer.pixelThreshold", the size, in pixels, under which
components/instances will not be displayeds.
* New: In CRL/etc/cmos.misc.py, added parameters "viewer.minimumSize"
and "viewer.pixelsThreshold".
Integrate new features and bug fixes so the Arlet 6502 benchs successfully
passes real DRC with reference industrial tools. Short summary:
* Manage minimum area for VIAs in Katana::Tracks.
* Allow different wire width for wires perpandicular to the prefered
routing direction.
* StackedVIAs used in the clock tree no longer assume an uniform
routing grid (same offset & pitch all the way up).
* Some hard-coded patches in PowerRails for FlexLib.
* New: In CRL/symbolic/cmos/kite.py & cmos45/kite.py, update the
RoutingLayerGauges by adding the new PWireWidth parameter.
Always zero in case of symbolic layout (too fine tuning).
* New: In CRL::RoutingGauge, add accessor to PWireWidth parameter.
Modify the clone method.
* New: In CRL::RoutingLayerGauge, add new parameter "PWireWidth"
to give the width of a wire when it not drawn in the prefered
routing direction. If it is set to zero, the normal width is
used.
* New: In CRL::PyRoutingGauge, export the updated constructor
interface. It is *not* backward compatible, one must add the
PWireWidth parameter in the various kite.py configuration
files (in etc/).
* Change: In AnabaticEngine::_gutAnabatic(), disable the minimum
area detection mechanism, replaced by a more complete one in
Katana::Track. Left commented out for now, but will be removed
in the future.
* Change: In Anabatic::AutoContact::updateLayer(), now systematically
calls setLayerAndWidth() to potentially resize the VIAs. This is
needed in real mode as VIAs are *not* macro-generated but have
their real final size.
* Change: In Anabatic::AutoContact::setLayerAndWidth(), select the
width and height of the contact using the gauge wire width *and*
perpandicular *wire width*.
* Change: In Anabatic::AutoSegment::_initialize(), the "VIA to same cap"
to PWireWidth/2, this will be the size of the VIA in the
non-preferred direction at the end cap (non-square in real mode).
* Change: In Anabatic::AutoSegment::getExtensionCap(), makes different
cases for symbolic and real. Use raw length in real, add half the
wire width in symbolic.
Add a flag to get the extension cap *only*, not increased of
half the minimal spacing.
* Change: In Anabatic::AutoSegment::bloatStackedStrap(), enhanced,
but finally unused...
* New: In Anabatic::AutoSegment::create(), use the PWireWidth when
the segment is not in the preferred routing direction (and of
minimal width).
* New: In Anabatic::Configuration, add new getPWirewidth(),
DPHorizontalWidth() and DPVerticalWidth() accessors.
* Change: In AnabaticEngine::setupPreRouteds(), skip components in
in "cut" material. We are only interested in objects containing
some metal (happens in real mode when VIAs cuts are really there).
* New: In Katana::PowerRailsPlanes::Rail::doLayout(), add an hard-coded
patch that artificially enlarge the *wide wire* so the spacing for
wide wire is enforced. For now, two pitches on each side for
"FlexLib" gauge.
* New: In Katana::Track, add support to find and correct small wire
chunks so they respect the minimum area rules.
Two helper functions:
* ::hasSameLayerTurn(), to find if a a TrackElement as non-zero length
perpandicular is same layer connected to it.
* ::toFoundryGrid(), to ensure that all coordinates will be on the
foundry grid (may move in a more shared location).
* ::expandToMinArea(), try to expand, *in the routing direction*
the too small wire so it respect the minimal area. Check for the
free space in the track.
Track::minExpandArea() go through all the TrackElements in the track
to look for too small ones and correct them.
* Change: In Katana::RoutingPlane, add an accessor to get the tracks.
* New: In KatanaEngine::finalizeLayout(), add a post-treatment to find
for minimal area violations.
* Change: In cumulus/plugins.block.configuration.GaugeConf, add a
routingBb attribute that will serve as a common reference to all
the functions calculation track positions. We must not have two
different reference for the core and the corona. The reference
is always the corona when we working on a complete chip.
* New: In cumulus/plugins.block.configuration.GaugeConf.getTrack(),
Simplified and more reliable way of getting tracks positions.
Use the routingBb.
* New: In cumulus/plugins.block.configuration.GaugeConf.rpAccess(),
Make use of getTrack() to get every metal strap on the right
X/Y position.
* New: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
As those wires are left alone by the router, it is our responsability
to abide by the minimal area rule here. Hence the code duplication
from the router (bad).
Mainly wires made for the clock tree, I mean.
* Bug: In cumulus/plugins.chip.configuration.ChipConf.setupICore(),
the core instance must be placed on the GCell grid, defined by the
slice height (X *and* Y).
* Bug: In cumulus/plugins.chip.corona.Builder(), forgot to use bigvia
for the corners of the inner ring.
* Bug: In cumulus/plugins.chip.pads.corona._createCoreWire(), hard-coded
patch for LibreSOCIO, the power/ground connectors toward the core
are too wide and can create DRC errors when put side by side.
Shrink them by the minimal distance.
* Bug: In CRL::GdsDriver::hasLayout(), a Cell was saved in the GDSII
stream only if it has a layout, but the check was not accurate
enough. In the Arlet6502, the whole core was missing.
Now check for the abscence of Plugs (not unfinished Nets) and
PLACED/FIXED instances.
* Change: In documentation/build.py, more PEP8 & Python 3 future compliance.
Correct copy of the tools HTML docs on my laptop, to have a full
offline copy of the doc.
* New: In documentation/contents/pages/check-toolkit, duplicate the doc
from alliance-check-toolkit README. Seems it has been inadvertently
removed at some point (?). Have to be careful to maintain in synch
with the toolkit.
* Change: <tool>/doc/*/SoC.css, use Roboto fonts when availables.
* Update: Commit the whole pre-generated docs (Doxygen, Pelican).
* Bug: In CRL/GdsStream::toGdsDbu(), when converting a physical number,
in double to a number of GDSII dbu in int32_t, we must not use the
direct cast int32_t(v) because v can be 2.9999999999 which got
simply truncated into 2 while we want 3. So now use the rounding
function std::lrint() and configure it round to the *nearest*
integer.
Note that we don't check that the long returned can correctly
fit into int32_t.
Jean-Paul Chaput
Luke Kenneth Casson Leighton
Staf Verhaegen