Commit Graph

1454 Commits

Author SHA1 Message Date
Jean-Paul Chaput d825a76252 Updated documentation, introduce Etesian & plugins. 2015-03-06 08:58:10 +01:00
Jean-Paul Chaput 2739d32bf8 Fix for Etesian build under Cygwin/W8 (N. Shmizu) 2015-03-04 11:11:12 +01:00
Jean-Paul Chaput f5020120bf Correct clock-tree building when used on a standalone block.
* Change: In Cumulus, in Configuration.py, in the horizontal & vertical
    wire creation adds new flags ExpandWidth to draw wires one lambda
    bigger than the minimal width (see ClockTree.py patch).
* Change: In Cumulus, In ClockTree.py, use non default width to draw
    wires of the H branch of the clock tree. This is to prevent them
    to be recognized as "manual global routing", which they are not
    and not event topologically compatible.
* Bug: In Kite, in BuildPowerRails, change the way clocks are detected
    when working on a single block (not a whole chip). Now look only
    in clock which are external and do not filter out already routed
    ones.
* Change: In KiteEngine, in createGlobalGraph(), systematically call
    flattenNets() so nets that are added after the first flattening
    in the placer are also flattened. The flattenNets() Cell method
    takes care of not flattening twice a net.
2015-03-03 11:11:22 +01:00
Jean-Paul Chaput 4d184c7a75 Added etesian.conf in ispd05 symbolic technology. 2015-03-02 23:44:55 +01:00
Jean-Paul Chaput bddf1ceef5 Ispd05 bookshelf parser bad scaling bug correction.
* Bug: In CRL Core, in Ispd05Bookshelf, as the pitch is already expressed
    in DbU, do not apply DbU::toLambda() in any expression where it is used.
* Change: In Etesian, In AddFeeds, do not try insert feeds if there is no
    cell feed avalaible.
2015-03-02 23:29:08 +01:00
Jean-Paul Chaput 58c78c5d78 Annoying dir_search problem with IMPORTEDS. 2015-02-28 17:07:44 +01:00
Jean-Paul Chaput 225f9093b5 Support Fedora OS in Builder as well as in coriolisEnv. 2015-02-28 10:30:28 +01:00
Jean-Paul Chaput 8566126acc Adding Configuration support to Etesian.
* Change: In Bootstrap & ccb, the coloquinte project is renamed into
    "importeds", it will be the home of all the externally
    devellopped softwares that are needed to build Coriolis.
      Add explicit support for Fedora ("Linux.fc") and uses
    site-packages, as everybody else.
* New: In CRL Core, in etc/, adds the configuration files for Etesian.
* New: In Etesian, activate the Configuration object. Now uses it's
    own configuration variables instead of borrowing those of
    Nimbus & Mauka.
* Change: In Documentation, updated User's Guide to present Etesian
    as the placer, instead of Mauka.
* Change: In Cumulus, slight change in ClokTreePlugin and ChipPlugin
    to match the new Etesian/Python interface.
2015-02-27 18:16:03 +01:00
Jean-Paul Chaput bd3984a313 Correctly manage clock net isolateds from the main clock.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
    a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
    given a path and a leaf net. This method is slow and must not be
    used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
    pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
    Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
    of clock nets was incomplete. The case of unrouted clock nets
    that where not connected to the top core clock net, like the
    one in the datapath registers was faulty. They were partly
    recognized as unrouteds and partly as blockage generating a
    routing deadlock: routage impossible due to blockage generated
    from itself...
* New: In Stratus1, add a buildModel() utility function to automate
    the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
2015-02-25 22:22:16 +01:00
Jean-Paul Chaput 64ea693d6d Etesian patch (G. Gouvine) for the latest Coloquinte. 2015-02-24 13:34:52 +01:00
Jean-Paul Chaput 6d366a08bc Etesian integration with Chip & ClockTree plugins.
* New: In Hurricane, in DebugSession, add a new method to activate the
    trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
    no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
    the flattening of the clock net(s). For more safety perform the
    DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
    DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
    needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
    if some cells are already placed. Typically the buffers of a clock
    tree.
      Pass the correct orienation to row_compatible_orientation().
      Do not try to add feeds in the ISPD05 benchmarks. For now the
    benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
    to be routed as an ordinary signal when the clock tree is not
    used.
* New: In Kite, in BuildPowerRails, management & detection for the
    pre-routed clock.
      In KiteEngine constructor, early initialization of the blockage
    net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
    configuration parameter 'clockTree.placerEngine' to select between
    Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
    in the vertical layer to prevent the router to use the vertical
    tracks in under the prower lines (for example, blockage in M3
    with power line M5).
      In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
    the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
    signals and *not* the power pad.
      Add more meaningful error messages if a pad global signal is
    not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
    that is *from the bottom of the cell AB* (not from 'zero').
2015-02-24 13:13:17 +01:00
Jean-Paul Chaput 3b343f08cf Bug in Python proxy deallocation. Update to latest Coloquinte.
* Bug: In Bootstrap, in coriolisEnv.py, check if devtoolset-2 is already
    active before launching it as a sub-shell.
* Bug: In Isobar, In PyHurricane.h, DBoDestroyAttribute() set the proxy
    pointer toward the C++ object to NULL. So when the Python object is
    deleted no double-deletion occurs on the C++ object.
      Add some more trace information in Python link/dealloc.
* Change: In CRL Core, in cyclop, make CMakeLists.txt automatically
    choose the right rule for linking the binary wether we use Qt 4 or
    Qt 5. Very irksome problem.
* New: In EtesianEngine::addFeed(), do not take into account instances
    that are not placed entirely inside the top cell abutment box (was
    causing a core dump).
* Bug: In Katabatic, in GCellQueue, correct a mismatch between a GCell
    set and the iterators used upon it.
* Bug: In Mauka, in Row & Surface correct a mismatch between a container
    and it's iterator.
* New: In Etesian, updated to work with the latest Coloquinte, patch
    contributed by G. Gouvine.
      Added EtesianEngine::setDefaultAb() to compute an abutment box if
    the Cell is completly unplaced.
* New: In cumulus, in ClockTree, now the placer can be configured to be
    either Mauka (slow simulated annealing) or Etesian (fast analytic).
    New setting 'clockTree.placerEngine' in plugin settings.
2015-02-13 23:38:55 +01:00
Jean-Paul Chaput 05ec238080 coriolisEnv.py must not start devtoolset-2 when already active. 2015-02-03 23:41:55 +01:00
Jean-Paul Chaput 4fd34a85a1 post-receive-email restauration test 2. 2015-02-02 00:39:49 +01:00
Jean-Paul Chaput f4e1dd1fb8 post-receive-email restauration test 1. 2015-02-02 00:35:44 +01:00
Jean-Paul Chaput b18219d807 Integration of the latest Coloquinte in Etesian & misc modifs.
* New: In Bootstrap, in Builder & coriolisEnv.py support for RHEL7/SL7.
    The sub-directory name is 'el7_64'.
      In qt_setup() add QtSvg to list of Qt5 & Qt4 used libraries.
* New: In Hurricane, In Cell add a placeholder for flags. First use to
    store whether the Nets have been transhierarchically flatteneds.
* New: In Hurricane, In NetRoutingState add an Unconnected flag for
    more accurate diagnosis.
* New: Hurricane, in CellViewer add an entry menu for stress tests.
    The script must be named "stressScript.py" in the cwd.
* Change: In CRL Core, in display.conf add a scaling parameter for the
    display threhold of the layer. This way we can adapt to different
    standard cells height.
* Change: In CRL Core, in ISPD05 bookshelf loader, use the pitch of the
    cell gauge instead of a hard-wired 5.0.
* Change: In Cumulus, in ClockTreePlugin, add support for Etesian placer
    and a new configuration parameter to choose between Mauka/Etesian.
* New: In Etesian, support for the latest Coloquinte.
    Add feed insertion stage.
* Bug: In Kite, In BuildPowerRails, check that _ck is not NULL before
    tring to access it's name...
* Change: In Kite, check if the Cell has it's Nets flattened before
    doing it (or not).
2015-02-01 23:24:13 +01:00
Jean-Paul Chaput 56bd484429 In BlockPower, manage correctly a block without clock tree. 2014-12-12 18:40:53 +01:00
Jean-Paul Chaput a09e716ce9 More talkative VST parser.
* Change: In CRL Core, in VstParserGrammar.yy display in which mode a file
    is read. Behavioral, structural or model. Model is the step of reading
    the instance's models before truly reading the file.
      In addition, a small optimization, when in behavioral mode, parse
    the file only once.
2014-12-12 18:40:12 +01:00
Jean-Paul Chaput 6fb56f43e7 Documentation update for MacOS. 2014-12-12 12:05:25 +01:00
Jean-Paul Chaput 8eac4b4b6f More robust VST parser.
* Bug: In CRL Core, in VstParserGrammar.yy & VstParserScanner.ll, accurate
    error message positions (file & line numbers).
      When generating error message, we cannot pass char* on variables that
    will be deallocated by the throw. So generate a string that will be
    copied along with the exception. That problems explain numerous
    core-dump when encountering syntaxes errors in the file.
2014-12-11 23:56:59 +01:00
Jean-Paul Chaput 978315c017 Compliance with Clang 3.4 (RHEL7, MacOS).
* New: In Bootstrap, added support for RHEL7 in ccb.py & coriolisEnv.py.
   In coriolisEnv.py, under RHEL6, directly launch a shell under
   devtoolset-2 (do not put it in .bashrc).
* Change: All tools, compliance with Clang 3.2.
   - Call using namespace std *after* at least one include of std has
     been used.
   - In Utilities.h define both const and non-cont overload for operator<<
     of mstream (this was the true cause of the Banner display problem).
   - No longer use defaults arguments in templates, instead create two
     separated overloads.
   - Put template static attributes allocation outside of namespaces
     (this one I'm not sure how to justify).
   - Protect by NDEBUG variables that are only needed in assert().
   - In PyInterval getUnion() & getIntersection() we where silently
     overwriting the "self" object (interval).
   - In Mauka, *do no* overload _postCreate() and add an argument, breaks
     the virtual function mechanism. Rename it into _maukaPostCreate().
     Idem for SubRow().
   - In Katabatic::GCell(), invalidate() overload a Go funtion but is
     used for different purpose at this level. Rename it invalidateCt()
     (invalidate *ConTents*).
   - Miscellaneous small cleanup.
2014-12-09 23:49:46 +01:00
Jean-Paul Chaput 37c8498962 Support for devtoolset-2, clang and c++11 improvement. 2014-12-05 18:50:15 +01:00
Jean-Paul Chaput b98e6a968a Kite, Pin are not pre-route, do not use _vdde when routing a block.
* Bug: In Kite, in KiteEngine::BuildPreRouteds(), Pin (sub-class of
    Contact) must not be considered as a component triggering the
    *already routed* state.
* Bug: In Kite, in BuildPreRouteds (GlobalNetTable), when de design
    is *not* a full chip, do not try to compare net with _vdde/_vsse.
2014-10-05 12:21:02 +02:00
Jean-Paul Chaput 60b0aa5ca7 Rename user's configuration (again), to use '.py' extentions.
* Change: In CRL Core, in coriolisInit.py user configuration files are
    now suffixed ".py" instead of ".conf" (for settings & techno).
2014-10-03 19:11:06 +02:00
Jean-Paul Chaput fddf11516a More accurate tests in Katabatic to stop whining about bad doglegs.
* Change: In Katabatic, in AutoSegment::canonize() and
    Session::_canonize() no longer tag Global as WeakGlobal also.
    This avoid to try to make dogleg on them when we shouldn't.
    They where staying WeakGlobal even when there were no longer
    connected to a global.
* Change: In Katabatic, in AutoSegment::makeDogleg(), suppress the
    bug for pad message when we are in the global routing stage.
    At that point it is allowed to make doglegs under the pads are
    they are "layer change" ones.
2014-10-03 19:00:02 +02:00
Jean-Paul Chaput dbf87493eb In Kite, Segments where not rescheduled in some cases of moveUp().
* Bug: In Kite, in TrackSegment::_postDogleg() when called through
    TrackSegment::moveUp(), if no dogleg are created, that is the
    segment is "pivoted up" (for example a M3 connected to only
    M4 that is pivoted to M5), the segment was *not* rescheduled as
    it ough to be. The end result was a M5 in a M3 track...
* Change: In Kite, in Track::checkOverlaps() in case of further
    problems, also check that TrackSegments and Track are in the
    same layer.
2014-10-03 16:04:12 +02:00
Jean-Paul Chaput 648b85226e Use rowend instead of tie in ClockTree for removed clock buffers.
* Bug: In Cumulus, in ClockTree.py, do not use "tie_x0" which is 2 pitch
    wide to fill the free space left by clock-tree removed (unused)
    buffers. If the buffer size width is odd (in pitch), it will left
    a gap in the WELL. That was the cause of DRC notch errors.
      Instead use "rowend_x0" which is one pitch wide.
      Should use the same mechanism as in Mauka InsertFeed.
2014-10-02 00:42:59 +02:00
Jean-Paul Chaput c244c9ce70 Group all the user configuration file under a ".coriolis/" directory.
* Change: In CRL Core, in coriolisInit.py now read the configuration
    files from a ".coriolis2/" directory. This is to avoid too many
    dot files in the user's directory. Files have also been renamed:
       .coriolis2.conf         ==>  .coriolis2/settings.conf
       .coriolis2_techno.conf  ==>  .coriolis2/techno.conf
* Change: In Kite, in kiteInit.py follow the same policy as CRL Core
    for configuration file.
       .coriolis2.kite.py      ==>  .coriolis2/kite.py
2014-09-27 17:40:35 +02:00
Jean-Paul Chaput 9c322501fe Version 0.2 of the RDS documentation (Symbolic & BIGVIA). 2014-09-26 22:55:55 +02:00
Jean-Paul Chaput 8e5ec7f8b7 In RoutingPad::setOnBestComponent() improved selection.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), in case of
    area equality, do not choose on id but the geometrically lowest one.
    Between two runs of the global router, it is not possible to
    maintain identical ids. This may leading to a change to the selected
    component, and a change of the GCell it in, which cause bad
    topologies when read by Katabatic.
2014-09-25 23:57:32 +02:00
Jean-Paul Chaput 1f9ae36554 Bug fixes for MOSIS SCMOS_DEEP support.
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
    from Katabatic. Needed for Knik to be able to access thoses
    informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
    case of identical area, select the component of lowest id.
    This should not be needed if the component ordering was fully
    deterministic as it should be (will investigate later).
      This is to ensure that the choosen component is always the
    same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
    the segments only if the topology is valid (no NULL in the
    cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
    if the topology is bad instead of trying to continue (and core
    dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
    net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
    name of the net in the *chip* netlist. Must use the later to make
    comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
    globally routed by Knik. That is which NetRoutingProperty is not
    *Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
    width extention to sligthy shrink the connector thus avoiding a
    notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
    trees for the leaf clocks, as it seems overconstrained for the
    router. First move was to lower them in M2/M3 (instead of M3/M4)
    but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
    hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
    in Alliance git, but I prefer to keep newest doc in Coriolis.
2014-09-21 16:44:37 +02:00
Jean-Paul Chaput 2c345c9033 Various improvement & bug correction in Katabatic & Kite.
* Bug: In Katabatic, in AutoContactTurn::cacheAttach() unset the
    "cache invalidated" flag *only* if the h1 & v1 component are
    sets. This is needed because we can attach *before* the first
    cache revalidation (in the initial building stage).
* Bug: In Katabatic, in AutoSegment::getPPitch() out of bound access
    of the top of the RoutingGauge, in case of a top layer segment
    with a spin top flag (maybe this shouldn't happen?).
* Change: In Kite, in SegmentFsm::conflictSolveByPlaceds() take
    account as conflicting other global, global, blockage *and*
    now fixeds.
* Change: In Cumulus, in px2mpx.py more accurate way of transforming
    the pad blockages.
2014-09-14 18:54:10 +02:00
Jean-Paul Chaput a3963716b1 Correction in plugins to support msxlib compatible pads.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
    variable to define the pad model name extension ("px" for "sxlib
    and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
    of used for power & clock supply. We may remove the extention in
    the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
    longer place the accessing contact *at the center* of the
    RoutingPad. It works under sxlib because buffers & registers all
    have same size terminals. But this is not true under vsxlib,
    leading to misaligned contacts & wires. Now systematically place
    on the slice midlle track (maybe with one pitch above or below).
      This is still very weak as we do not check if the terminal
    reach were the contact is being put. Has to be strenthened in
    the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
    clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
    of PyInt for DbU conversions. In PyHurricane argument converter,
    automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
    in case of discrepency in global net connections (i.e. no net
    of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
    model name to find "pck_" or "pvddeck_", do not compare the
    extension part. But we still use hard-coded stem pad names,
    maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
    was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
    RoutingPads of fixed nets, they are already through the
    BuildPowerRails stage (and it's causing scary overlap warning
    messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
    deep-plug when the core is flat (not sub-modules). All the new
    nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
    that the core is aligned on the GCell grid (i.e. the slice
    grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
    while looking for the bigger N-E RoutingPad. Forgot to decrement
    the index...
2014-09-13 17:45:30 +02:00
Jean-Paul Chaput f85159bdb4 More accurate error message in Python module importation. 2014-09-07 23:16:04 +02:00
Jean-Paul Chaput c26a36db88 In ChipPlugin, do not call the editor if it's not there. 2014-09-04 10:59:09 +02:00
Jean-Paul Chaput e6c809a12a Correct loading of clock buffer in ClockTree plugin.
* Bug: In ClockTree plugin, only the logical view of the clock buffer
    was loaded, so no external components where found on the I/O nets.
    The external components are loaded only when the *physical* view
    is loaded. Didn't show on sxlib because the buffer was fulled
    loaded *before* running the ClockTree.
* Bug: In PyHurricane, in the various LocatorNextMethod() macros,
    sometimes an empty collection can be returned by Hurricane
    (GenericCollection()), which has a NULL locator. So check
    if the locator is *not* NULL before trying to access it...
* Change: In Chip, more accurate error messages related to the clock
    detecttion.
2014-09-03 10:37:11 +02:00
Jean-Paul Chaput ae4d938553 Buffer cell configuration in ClockTree. More config parameters in Chip.
* New: In ClockTree plugin, select the name of the buffer cell through
    configuration (parameter: "clockTree.buffer"), and guess the I/O
    name of this buffer automatically.
      Put configuration parameters in plugin.conf and not mauka.conf.
      Bug: strangely triggers a coredump in components collection
    when used with <vsxlib>. Some debug printing still active until
    that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
    configuration parameters (in plugin.conf).
2014-09-02 11:17:47 +02:00
Jean-Paul Chaput 51a3236962 Add management of fixed wires to Kite (for chip ClockTree)
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
    variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
    is copied up as blockage. Uses blockage layer instead of true layer
    (it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
    nets with only default wiring (default size wire & contacts).
    Non-default routing is flagged as fixed (with the NetRoutingState
    property).
2014-08-15 19:26:49 +02:00
Jean-Paul Chaput fb4a7457a1 First basic version of ClockTree & Chip plugins.
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
    Clock Tree plugin:
    - It is strongly advised to use have 4 metal routing layers for the
      tree to work. Otherwise, problems can arise with the detailed
      routing (fully obstructed terminals).
    - H-Tree can only be build (for now) for design with a form factor
      between 0.5 an 2.
    - The tree is created at the block top-level and only the leafs are
      trans-hierarchically created on the instances/models. The new
      cell with a clock tree, along with all it's sub-models is created
      with a "_clocked" suffix.
    - Leaf cells are connected through a simple Minimum Steiner Tree.
    - Shorts are avoided by a systematic shift of the wires according
      to their kind. No wire must pre-exist. When used as a sub-module
      of "chip" the wires cannot be moved. When created on a block,
      the wires can be loaded in the detailed router as manual global
      router.
    Chip Plugin:
    - Perform the pad placement and corona creation. Replacement at
      last of the clunky code from Wu Yifei.
    - Relies on a Python configuration file '<design>_chip.py' with
      a "chip" dictionnary.
2014-08-15 19:05:27 +02:00
Jean-Paul Chaput 20f8d004e2 In ACSII/GDS driver, process the complete hierarchy.
* Bug: In CRL Core, in agdsDriver, the flags of the Query where sets to
   process only the top-level Cell. Now process the whole hierarchy (the
   Cell is completly flattened by this operation). Secondary bug: the
   transformation was not applied to the bounding boxes, resulting of
   all the cells stacked in (0,0) ...
2014-08-15 11:48:41 +02:00
Jean-Paul Chaput 4cf6bef950 Replace, again HUGE by HUGE_VAL in Knik (for Cygwin). 2014-08-06 17:44:07 +02:00
Jean-Paul Chaput 6d7dad54d1 In CellView, correct signal/slot toggle parameter. 2014-08-03 17:20:44 +02:00
Jean-Paul Chaput 6588902780 Correct edge capacity display in debug mode. 2014-08-03 16:38:57 +02:00
Jean-Paul Chaput fbeef95c0f Added support for MOSIS 180nm SCMOS technology (SCN6M_DEEP).
* New: In CRL Core, added configuration for SCMOS_DEEP symbolic technology
   up to 180nm "scmos_deep_018". It is postfixed "_018" because it is not
   yet compliant with 130nm (asymetrical VIA metal extensions).
     Added the associated real technology SCN6M_DEEP (TSMC 180nm).
2014-08-03 16:36:21 +02:00
Jean-Paul Chaput e5f3f5d89a Unsolved bug, add_definitions() doesn't work in Etesian CMakeLists.txt
* Bug: In Etesian CMakeLists.txt cannot get add_definitions() to work
   to enable/disable Coloquinte. As a workaroud, it's moved into the
   FindCOLOQUINTE.cmake itself. Cannot make any sense of it.
2014-08-03 16:30:36 +02:00
Jean-Paul Chaput f434ea4faa cgt now returns correct success/failure value to the UNIX shell. 2014-08-03 16:27:19 +02:00
Jean-Paul Chaput 206309ddd9 No longer directly use C++ exported symbols in configuration files.
* Change: In CRL Core, in Alliance.py, no longer requires the
    configuration file to uses symbols from CRL.Environment or
    CRL.RoutingLayerGauge. This way the <alliance.conf> file can be
    parsed by a different parser.
      In <alliance.conf>, for the various technologies, make uses
    of the new C++ independent constants.
* New: In CRL Core, in helpers/__init__.py, provide a "Dots" class
    (rewrite the C++ one in pure Python).
2014-08-03 16:25:26 +02:00
Jean-Paul Chaput b081d07bfc More strict detection of the configuration files install directory.
* Change: In Bootstrap, in FindBoostrap.cmake, install in system-wide
    directories /etc or /opt only if the the installation path is
    exactly /usr or /opt and not only beginning with it.
2014-08-03 16:17:13 +02:00
Jean-Paul Chaput 51a1615d92 Do not display H/V edge capacity on one column/row design. 2014-08-01 17:22:06 +02:00
Jean-Paul Chaput e01f943367 Added ASCII/GDSII export capability in Unicorn.
* New: In Unicorn, in ExportCellDialog and UnicornGui add an entry to
    call the ASCII/GDSII export driver.
* New: In CRL Core, in AgdsDriver, checks for off-grid coordinates (that
    is non-integer one) and round them with a warning. This is most
    likely that the layout is flawed but it will at leat generate a
    readable ASCII/GDSII file.
2014-07-31 19:40:23 +02:00