Updated documentation, introduce Etesian & plugins.

This commit is contained in:
Jean-Paul Chaput 2015-03-06 08:58:10 +01:00
parent 2739d32bf8
commit d825a76252
22 changed files with 2196 additions and 500 deletions

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@ -10,26 +10,6 @@
.. _Here: file:///usr/share/doc/coriolis2/en/latex/users-guide/UsersGuide.pdf
.. For HTML backend
.. |Key_ESC| image:: ./images/key_ESC.png
.. |Key_CTRL| image:: ./images/key_CTRL.png
.. |Key_Up| image:: ./images/key_UP.png
.. |Key_Down| image:: ./images/key_DOWN.png
.. |Key_Left| image:: ./images/key_LEFT.png
.. |Key_Right| image:: ./images/key_RIGHT.png
.. |Key_f| image:: ./images/key_F.png
.. |Key_G| image:: ./images/key_Gcap.png
.. |Key_i| image:: ./images/key_Icap.png
.. |Key_l| image:: ./images/key_Lcap.png
.. |Key_m| image:: ./images/key_M.png
.. |Key_k| image:: ./images/key_K.png
.. |Key_K| image:: ./images/key_Kcap.png
.. |Key_o| image:: ./images/key_Ocap.png
.. |Key_p| image:: ./images/key_Pcap.png
.. |Key_q| image:: ./images/key_Qcap.png
.. |Key_w| image:: ./images/key_Wcap.png
.. |Key_S| image:: ./images/key_Scap.png
.. |Key_z| image:: ./images/key_Z.png
.. |Plus| replace:: :raw-html:`+`
.. |rightarrow| replace:: :raw-html:`<p class="empty"></p>`
.. |menu_P&R| replace:: :raw-html:`<p class="empty"></p>`
.. |menu_StepByStep| replace:: :raw-html:`<p class="empty"></p>`
@ -54,6 +34,8 @@
.. |ControllerInspector_3| replace:: :raw-html:`<center><img src="./images/Controller-Inspector-3.png" alt="Controller Basic Snapshot"></center>`
.. |ControllerSettings_1| replace:: :raw-html:`<center><img src="./images/Controller-Settings-1.png" alt="Controller Basic Snapshot"></center>`
.. |CoriolisSoftSchema| replace:: :raw-html:`<center><img src="./images/Coriolis-Soft-Schema.png" alt="Coriolis Software Schematic"></center>`
.. |ChipStructure-1| replace:: :raw-html:`<center><img src="./images/chip-structure-1.png" alt="Chip Top Structure"></center>`
.. |Etesian-1| replace:: :raw-html:`<center><img src="./images/etesian-1.png" alt="Etesian Abutment Box"></center>`
.. |BigMouse| image:: ./images/ComputerMouse.png
:scale: 25%
@ -63,4 +45,5 @@
.. |noindent| replace:: :raw-html:`<p class="empty"></p>`
.. |medskip| replace:: :raw-html:`<br>`
.. |newpage| replace:: :raw-html:`<hr>`
.. |br| replace:: :raw-html:`<br>`

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@ -11,26 +11,6 @@
.. |DONE| replace:: :raw-latex:`\marginpar{\fbox{\small\ding{56}}}`
.. For LaTeX/PDF backend.
.. |Key_ESC| replace:: :raw-latex:`\key{ESC}\xspace`
.. |Key_CTRL| replace:: :raw-latex:`\key{CTRL}\xspace`
.. |Key_Up| replace:: :raw-latex:`\key{Up}\xspace`
.. |Key_Down| replace:: :raw-latex:`\key{Down}\xspace`
.. |Key_Left| replace:: :raw-latex:`\key{Left}\xspace`
.. |Key_Right| replace:: :raw-latex:`\key{Right}\xspace`
.. |Key_f| replace:: :raw-latex:`\key{f}\xspace`
.. |Key_G| replace:: :raw-latex:`\key{G}\xspace`
.. |Key_i| replace:: :raw-latex:`\key{i}\xspace`
.. |Key_l| replace:: :raw-latex:`\key{l}\xspace`
.. |Key_m| replace:: :raw-latex:`\key{m}\xspace`
.. |Key_k| replace:: :raw-latex:`\key{k}\xspace`
.. |Key_K| replace:: :raw-latex:`\key{K}\xspace`
.. |Key_o| replace:: :raw-latex:`\key{o}\xspace`
.. |Key_p| replace:: :raw-latex:`\key{p}\xspace`
.. |Key_q| replace:: :raw-latex:`\key{q}\xspace`
.. |Key_w| replace:: :raw-latex:`\key{w}\xspace`
.. |Key_S| replace:: :raw-latex:`\key{S}\xspace`
.. |Key_z| replace:: :raw-latex:`\key{z}\xspace`
.. |Plus| replace:: :raw-latex:`$+$\xspace`
.. |rightarrow| replace:: :raw-latex:`$\rightarrow$`
.. |menu_P&R| replace:: :raw-latex:`\fbox{\textsf{\textbf{{P\&R}}}}`
.. |menu_StepByStep| replace:: :raw-latex:`\fbox{\textsf{\textbf{{\underline{S}tep by Step}}}}`
@ -55,6 +35,8 @@
.. |ControllerInspector_3| replace:: :raw-latex:`\begin{center}\includegraphics[width=.7\textwidth]{./images/Controller-Inspector-3.eps}\end{center}`
.. |ControllerSettings_1| replace:: :raw-latex:`\begin{center}\includegraphics[width=.7\textwidth]{./images/Controller-Settings-1.eps}\end{center}`
.. |CoriolisSoftSchema| replace:: :raw-latex:`\begin{center}\includegraphics[width=.7\textwidth]{./images/Coriolis-Soft-Schema.eps}\end{center}`
.. |ChipStructure-1| replace:: :raw-latex:`\begin{center}\includegraphics[width=.95\textwidth]{./images/chip-structure-1.eps}\end{center}`
.. |Etesian-1| replace:: :raw-latex:`\begin{center}\includegraphics[width=.95\textwidth]{./images/etesian-1.eps}\end{center}`
.. |BigMouse| image:: ./images/ComputerMouse.eps
:scale: 25%
@ -64,4 +46,5 @@
.. |noindent| replace:: :raw-latex:`\noindent`
.. |medskip| replace:: :raw-latex:`\medskip`
.. |newpage| replace:: :raw-latex:`\newpage`
.. |br| replace:: :raw-latex:`\\`

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@ -1,10 +1,7 @@
html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 {
font-size: 96%;
/*
font-family: verdana, sans-serif;
*/
font-family: "Open Sans", sans-serif;
font-family: "Open Sans", verdana, sans-serif;
}
body {
@ -18,9 +15,13 @@ body {
background-attachment: fixed;
background-repeat: no-repeat;
margin: 0 0 0 0;
padding: 0 0 0 0;
padding: 20pt;
width: 550pt;
margin-right: 10%;
margin-left: 30%;
-moz-box-shadow: 4px 4px 5px 3px #ccc;
-webkit-box-shadow: 4px 4px 5px 3px #ccc;
box-shadow: 4px 4px 5px 3px #ccc;
}
body.gsummary {
@ -28,22 +29,27 @@ body.gsummary {
margin-left: 10%;
}
h1, h2, h3, h4, h5, h6 {
font-family: "Open Sans", sans-serif;
}
h1, h2, h3, h4, h5, h6 { font-family: "Open Sans", verdana, sans-serif; }
h1 { text-align: center;
border-top: 2px solid #09550b;
border-bottom: 2px solid #09550b;
padding-top: 7pt;
padding-bottom: 7pt;
}
h2, h3, h4, h5, h6 { text-align: left; }
h1, h2, h3 { font-family: "Open Sans";
}
h1 { font-weight: normal; font-size: 170%; padding-top: 7pt; margin-top: 25pt; }
h2 { font-weight: normal; font-size: 140%; padding-top: 7pt; margin-top: 25pt; }
h3 { font-weight: bold; font-size: 118%; padding-top: 7pt; margin-top: 25pt; }
h4 { font-weight: bold; font-size: 100%; }
h5 { font-style: italic; font-size: 100%; }
h6 { font-variant: small-caps; font-size: 100%; }
body.gsummary h1 { text-align: center; font-size: 220%; }
h1 a:link { border-bottom: 0px; }
h1 { text-align: left; }
h2, h3, h4, h5, h6 { text-align: left; }
h1, h2, h3 { font-family: "Serif";
}
h1 { font-weight: normal; font-size: 170%; padding-top: 7pt; margin-top: 25pt; }
h2 { font-weight: normal; font-size: 140%; padding-top: 7pt; margin-top: 25pt; }
h3 { font-weight: bold; font-size: 118%; padding-top: 7pt; margin-top: 25pt; }
h4 { font-weight: bold; font-size: 100%; }
h5 { font-style: italic; font-size: 100%; }
h6 { font-variant: small-caps; font-size: 100%; }
body.gsummary h1 { text-align: center; font-size: 220%; }
hr {
color: #09550b;

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@ -27,6 +27,8 @@
.. |FC13| replace:: :sc:`fc13`
.. |Debian| replace:: :sc:`Debian`
.. |Ubuntu| replace:: :sc:`Ubuntu`
.. |LEMON| replace:: :sc:`lemon`
.. |Coin-Or| replace:: :sc:`coin-or`
.. |Alexandre| replace:: :sc:`Alexandre`
.. |Belloeil| replace:: :sc:`Belloeil`
@ -89,13 +91,43 @@
.. |rpm| replace:: :cb:`rpm`
.. |gdb| replace:: :cb:`gdb`
.. |KeyUp| replace:: :fboxtt:`Up`
.. |KeyDown| replace:: :fboxtt:`Down`
.. |KeyLeft| replace:: :fboxtt:`Left`
.. |KeyRight| replace:: :fboxtt:`Right`
.. |KeyF| replace:: :fboxtt:`f`
.. |KeyL| replace:: :fboxtt:`l`
.. |KeyG| replace:: :fboxtt:`g`
.. |KeyZ| replace:: :fboxtt:`z`
.. |KeyM| replace:: :fboxtt:`m`
.. |KeyI| replace:: :fboxtt:`i`
.. |KeyK| replace:: :fboxtt:`k`
.. |KeyP| replace:: :fboxtt:`p`
.. |KeyO| replace:: :fboxtt:`o`
.. |KeyW| replace:: :fboxtt:`w`
.. |KeyQ| replace:: :fboxtt:`q`
.. |KeyCapK| replace:: :fboxtt:`K`
.. |KeyCapS| replace:: :fboxtt:`S`
.. |Plus| replace:: :fboxtt:`+`
.. |KeyESC| replace:: :fboxtt:`ESC`
.. |CTRL| replace:: :fboxtt:`CTRL`
.. |CTRL_L| replace:: :fboxtt:`CTRL+L`
.. |CTRL_I| replace:: :fboxtt:`CTRL+I`
.. |CTRL_P| replace:: :fboxtt:`CTRL+P`
.. |CTRL_O| replace:: :fboxtt:`CTRL+O`
.. |CTRL_W| replace:: :fboxtt:`CTRL+W`
.. |CTRL_Q| replace:: :fboxtt:`CTRL+Q`
.. |CTRL_Down| replace:: :fboxtt:`CTRL+Down`
.. |CTRL_Up| replace:: :fboxtt:`CTRL+Up`
.. |CTRL_Left| replace:: :fboxtt:`CTRL+Left`
.. |CTRL_Right| replace:: :fboxtt:`CTRL+Right`
.. URLs
.. _FGR: http://vlsicad.eecs.umich.edu/BK/FGR/
.. _Box Router: http://www.cerc.utexas.edu/~thyeros/boxrouter/boxrouter.htm
.. _hMETIS: http://glaros.dtc.umn.edu/gkhome/views/metis
.. _Knik Thesis: http://www-soc.lip6.fr/en/users/damiendupuis/PhD/
.. _FGR: http://vlsicad.eecs.umich.edu/BK/FGR/
.. _Box Router: http://www.cerc.utexas.edu/~thyeros/boxrouter/boxrouter.htm
.. _hMETIS: http://glaros.dtc.umn.edu/gkhome/views/metis
.. _Knik Thesis: http://www-soc.lip6.fr/en/users/damiendupuis/PhD/
.. _Coin Or Home: http://www.coin-or.org/index.html
.. _coriolis2-1.0.2049-1.slsoc6.i686.rpm: http://asim.lip6.fr/pub/coriolis/2.0/coriolis2-1.0.2049-1.slsoc6.i686.rpm
.. _coriolis2-1.0.2049-1.slsoc6.x86_64.rpm: http://asim.lip6.fr/pub/coriolis/2.0/coriolis2-1.0.2049-1.slsoc6.x86_64.rpm
@ -274,8 +306,8 @@ Release `2049` is Alpha.
#. The |cgt| main has been rewritten in Python.
Release **v2.0.1**
~~~~~~~~~~~~~~~~~~
Release v2.0.1
~~~~~~~~~~~~~~
#. Migrated the repository from |svn| to |git|, and release complete sources.
As a consequence, we drop the distribution packaging support and give
@ -284,7 +316,7 @@ Release **v2.0.1**
achieve a speedup factor greater than 20...
Release **v3.0**
**Release v2.1**
~~~~~~~~~~~~~~~~
#. Replace the old simulated annealing placer |Mauka| by an analytic placer
@ -325,6 +357,17 @@ Main building prerequisites:
* latex
* latex2html.
* python-docutils (for reStructuredText).
* |Coloquinte| (https://github.com/Coloquinte/Coloquinte.git).
|Coloquinte| requires the |LEMON| component from |Coin-Or| (`Coin Or Home`_).
A repository of |Coin-Or| packages backported from |Fedora| 21 is available here:
* |SL6|: `ftp://pub/linux/distributions/slsoc/slsoc/soc/addons/i386/RPMS <http://ftp.lip6.fr/pub/linux/distributions/slsoc/slsoc/soc/addons/i386/repoview>`_
* |SL7|: `ftp://pub/linux/distributions/slsoc/soc/7/addons/x86_64/RPMS <http://ftp.lip6.fr/pub/linux/distributions/slsoc/soc/7/addons/x86_64/repoview>`_
For other distributions, refer to their own packaging system.
|newpage|
Fixed Directory Tree
@ -378,6 +421,8 @@ automatically created either by |ccb| or the build system.
``Static`` do not work because I don't know yet to mix statically linked binaries
and Python modules (which must be dynamic).
|newpage|
Building Coriolis
~~~~~~~~~~~~~~~~~
@ -394,9 +439,11 @@ The first step is to create the source directory and pull the |git| repository:
Second and final step, build & install: ::
dummy@lepka:src$ ./bootstrap/ccp.py --project=importeds --project=coriolis \
dummy@lepka:src$ ./bootstrap/ccp.py --project=importeds \
--project=coriolis \
--make="-j4 install"
dummy@lepka:src$ ./bootstrap/ccb.py --project=coriolis --doc --make="-j1 install"
dummy@lepka:src$ ./bootstrap/ccb.py --project=coriolis \
--doc --make="-j1 install"
We need two steps because the documentation do not support to be generated with
a parallel build. So we compile & install in a first step in ``-j4`` (or whatever)
@ -404,7 +451,8 @@ then we generate the documentation in ``-j1``
Under |RHEL6| or clones, you must build using the |devtoolset2|: ::
dummy@lepka:src$ ./bootstrap/ccp.py --project=importeds --project=coriolis \
dummy@lepka:src$ ./bootstrap/ccp.py --project=importeds \
--project=coriolis \
--devtoolset-2 --make="-j4 install"
If you want to uses Qt 5 instead of Qt 4, you may add the ``--qt5`` argument.
@ -426,7 +474,8 @@ In the |Coriolis| |git| repository, two branches are present:
command just after the first step: ::
dummy@lepka:~$ git checkout devel
dummy@lepka:src$ ./bootstrap/ccp.py --project=importeds --project=coriolis \
dummy@lepka:src$ ./bootstrap/ccp.py --project=importeds \
--project=coriolis \
--make="-j4 install" --debug
Be aware that it may requires newer versions of the dependencies and may introduce
@ -437,6 +486,8 @@ In the |Coriolis| |git| repository, two branches are present:
dummy@lepka:work$ gdb python core.XXXX
|newpage|
Additionnal Requirement under |MacOS|
-------------------------------------
@ -615,6 +666,8 @@ simple assembly of tuples. The helpers are installed under the directory: ::
Where :cb:`<install>/` is the root of the installation.
|newpage|
.. _Alliance Helper:
@ -909,14 +962,40 @@ Etesian -- Placer
~~~~~~~~~~~~~~~~~
The |Etesian| placer is a state of the art (as of 2015) analytical placer. This |Coriolis|
tool is really an encapsulation of |Coloquinte| which *is* the placer. |Coloquinte|
is provided a separate library, see the building instructions.
tool is actually an encapsulation of |Coloquinte| which *is* the placer. |Coloquinte|
is provided as a separate library, see the building instructions.
.. note:: *Instance Duplication Problem:* a same logical instance cannot have
.. note:: *Instance Uniquification Unsupported:* a same logical instance cannot have
two different placements. So, either you manually make a clone of it or you
supply a placement for it. This is currently a drawback of our *folded hierarchy*
approach.
supply a placement for it. We need to implement uniquification in the
|Hurricane| database.
|noindent|
**Hierarchical Placement**
The placement area is defined by the top cell abutment box.
When placing a complete hierarchy, the abutment boxes of the cells (models) other than
the top cell are sets identical to the one of the top cell and their instances are
all placed at position ``(0,0,ID)``. That is, all the abutments boxes, whatever the
hierarchical level, defines the same area (they are exactly superposed).
We choose this scheme because the placer will see all the instances as virtually
flattened, so they can be placed anywhere inside the top-cell abutment box.
|Etesian-1|
|noindent|
**Computing the Placement Area**
The placement area is computed using the ``etesian.aspectRatio`` and ``etesian.spaceMargin``
parameters only if the top-cell has an empty abutment box. If the top-cell abutment
box has to be set, then it is propagated to all the instances models recursively.
|noindent|
**Reseting the Placement**
Once a placement has been done, the placer cannot reset it (will be implemented
@ -924,6 +1003,48 @@ later). To perform a new placement, you must restart |cgt|. In addition, if you
have saved the placement on disk, you must erase any :cb:`.ap` file, which are
automatically reloaded along with the netlist (:cb:`.vst`).
|newpage|
Etesian Configuration Parameters
--------------------------------
+-----------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+===================================+==================+============================+
| **Etesian Parameters** |
+-----------------------------------+------------------+----------------------------+
|``etesian.aspectRatio`` | TypePercentage | :cb:`100` |
| +------------------+----------------------------+
| | Define the height on width ``H/W`` aspect |
| | ratio, can be comprised between 10 and 1000 |
+-----------------------------------+------------------+----------------------------+
|``etesian.spaceMargin`` | TypePercentage | :cb:`5` |
| +------------------+----------------------------+
| | The extra white space added to the total area |
| | of the standard cells |
+-----------------------------------+------------------+----------------------------+
|``etesian.uniformDensity`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | Whether the cells will be spread envenly |
| | across the area or allowed to form denser |
| | clusters |
+-----------------------------------+------------------+----------------------------+
|``etesian.effort`` | TypeInt | :cb:`2` |
| +------------------+----------------------------+
| | Sets the balance between the speed of the |
| | placer and the solution quality |
+-----------------------------------+------------------+----------------------------+
|``etesian.graphics`` | TypeInt | :cb:`2` |
| +------------------+----------------------------+
| | How often the display will be refreshed, more |
| | refreshing slows the placer. |
| | |
| | * ``1`` show both upper and lower bounds |
| | * ``2`` show only lower bound |
| | * ``3`` Don't show anything |
+-----------------------------------+-----------------------------------------------+
Knik -- Global Router
~~~~~~~~~~~~~~~~~~~~~
@ -976,8 +1097,6 @@ saturated area and increased wirelength. This is the saturation of the
which represent one track. The maximum capacity of the |SxLib| gauge is
10 tracks in two layers, that makes 20 tracks by |Knik| edge.
|newpage|
Routing a design is done in four ordered steps:
#. Detailed pre-route |menu_P&R| |rightarrow| |menu_StepByStep| |rightarrow| |menu_KiteDetailedPreRoute|.
@ -1125,7 +1244,7 @@ Printing & Snapshots
~~~~~~~~~~~~~~~~~~~~
Printing or saving into a |pdf| is fairly simple, just uses the **File -> Print**
menu or the |Key_CTRL| |Plus| |Key_p| shortcut to open the dialog box.
menu or the |CTRL_P| shortcut to open the dialog box.
The print functionality uses exactly the same rendering mechanism as for the
screen, beeing almost *WYSIWYG*. Thus, to obtain the best results it is advisable
@ -1162,22 +1281,21 @@ The main application binary is |cgt|.
+---------------+-------------------+-----------------------------------------------------------+
| Category | Keys | Action |
+===============+===================+===========================================================+
| **Moves** | | |Key_Up|, | Shift the view in the according direction |
| | |Key_Down| | |
| | | |Key_Left|, | |
| | |Key_Right| | |
| **Moves** | | |KeyUp|, | Shift the view in the according direction |
| | |KeyDown| | |
| | | |KeyLeft|, | |
| | |KeyRight| | |
+---------------+-------------------+-----------------------------------------------------------+
| **Fit** | |Key_f| | Fit to the Cell abutment box |
| **Fit** | |KeyF| | Fit to the Cell abutment box |
+---------------+-------------------+-----------------------------------------------------------+
| **Refresh** | |Key_CTRL| | Triggers a complete display redraw |
| | |Plus| |Key_l| | |
| **Refresh** | |CTRL_L| | Triggers a complete display redraw |
+---------------+-------------------+-----------------------------------------------------------+
| **Goto** | |Key_g| | *apperture* is the minimum side of the area |
| **Goto** | |KeyG| | *apperture* is the minimum side of the area |
| | | displayed around the point to go to. It's an |
| | | alternative way of setting the zoom level |
+---------------+-------------------+-----------------------------------------------------------+
| **Zoom** | |Key_z|, | Respectively zoom by a 2 factor and *unzoom* |
| | |Key_m| | by a 2 factor |
| **Zoom** | |KeyZ|, | Respectively zoom by a 2 factor and *unzoom* |
| | |KeyM| | by a 2 factor |
| +-------------------+-----------------------------------------------------------+
| | | |BigMouse| | You can perform a zoom to an area. |
| | | Area Zoom | Define the zoom area by *holding down the left |
@ -1188,52 +1306,51 @@ The main application binary is |cgt|.
| | | right mouse button* while moving the mouse. |
| +-------------------+-----------------------------------------------------------+
| | | |BigMouse| | You can toggle the selection of one object under |
| | | Toggle Selection| the mouse position by pressing |key_CTRL| and |
| | | Toggle Selection| the mouse position by pressing |CTRL| and |
| | | pressing down *the right mouse button*. A popup |
| | | list of what's under the position shows up into |
| | | which you can toggle the selection state of one |
| | | item. |
| +-------------------+-----------------------------------------------------------+
| | |Key_S| | Toggle the selection visibility |
| | |KeyCapS| | Toggle the selection visibility |
+---------------+-------------------+-----------------------------------------------------------+
| **Controller**| |Key_CTRL| | Show/hide the controller window. |
| | |Plus| |Key_i| | |
| **Controller**| |CTRL_I| | Show/hide the controller window. |
| | | |
| | | It's the Swiss Army Knife of the viewer. |
| | | From it, you can fine-control the display and |
| | | inspect almost everything in your design. |
+---------------+-------------------+-----------------------------------------------------------+
| **Rulers** | |Key_k|, | One stroke on |Key_k| enters the ruler mode, in |
| | |Key_ESC| | which you can draw one ruler. You can exit the |
| | | ruler mode by pressing |Key_ESC|. Once in ruler |
| **Rulers** | |KeyK|, | One stroke on |KeyK| enters the ruler mode, in |
| | |KeyESC| | which you can draw one ruler. You can exit the |
| | | ruler mode by pressing |KeyESC|. Once in ruler |
| | | mode, the first click on the *left mouse button* |
| | | sets the ruler's starting point and the second |
| | | click the ruler's end point. The second click |
| | | exits automatically the ruler mode. |
| +-------------------+-----------------------------------------------------------+
| | |Key_K| | Clears all the drawn rulers |
| | |KeyCapK| | Clears all the drawn rulers |
+---------------+-------------------+-----------------------------------------------------------+
| **Print** | |Key_CTRL| | Currently rather crude. It's a direct copy of |
| | |Plus| |Key_p| | what's displayed in pixels. So the resulting |
| **Print** | |CTRL_P| | Currently rather crude. It's a direct copy of |
| | | what's displayed in pixels. So the resulting |
| | | picture will be a little blurred due to |
| | | anti-aliasing mechanism. |
+---------------+-------------------+-----------------------------------------------------------+
| **Open/Close**| |Key_CTRL| | Opens a new design. The design name must be |
| | |Plus| |Key_o| | given without path or extention. |
| **Open/Close**| |CTRL_O| | Opens a new design. The design name must be |
| | | given without path or extention. |
| +-------------------+-----------------------------------------------------------+
| | |Key_CTRL| | Close the current viewer window, but do not quit |
| | |Plus| |Key_w| | the application. |
| | |CTRL_W| | Close the current viewer window, but do not quit |
| | | the application. |
| +-------------------+-----------------------------------------------------------+
| | |Key_CTRL| | `CTRL+Q` quit the application |
| | |Plus| |Key_q| | (closing all windows). |
| | |CTRL_Q| | `CTRL+Q` quit the application |
| | | (closing all windows). |
+---------------+-------------------+-----------------------------------------------------------+
| **Hierarchy** | |Key_CTRL| |Plus| | Go one hierarchy level down. That is, if there |
| | |Key_Down| | is an *instance* under the cursor position, load |
| **Hierarchy** | |CTRL_Down| | Go one hierarchy level down. That is, if there |
| | | is an *instance* under the cursor position, load |
| | | it's *model* Cell in place of the current one. |
| +-------------------+-----------------------------------------------------------+
| | |Key_CTRL| |Plus| | Go one hierarchy level up. if we have entered |
| | |Key_Up| | the current model through |Key_CTRL| |Plus| |
| | | |Key_Down|, reload the previous model (the one |
| | |CTRL_Up| | Go one hierarchy level up. if we have entered |
| | | the current model through |CTRL_Down| |
| | | reload the previous model (the one |
| | | in which this model is instanciated). |
+---------------+-------------------+-----------------------------------------------------------+
@ -1348,6 +1465,9 @@ Miscellaneous Settings
| | To generate one set this flag to :cb:`True` |
+---------------------------------------+------------------+----------------------------+
|newpage|
.. _The Controller:
The Controller
@ -1579,11 +1699,249 @@ This typical script can be executed in two ways:
+----------------------+-----------------------------------------------+
Plugins
=======
Plugins are |Python| scripts specially crafted to integrate with |cgt|.
Their entry point is a :cb:`ScriptMain()` method as described in
`Python Interface to Coriolis`_. They can be called by user scripts
through this method.
Chip Placement
~~~~~~~~~~~~~~
Automatically perform the placement of a complete chip. This plugin, as well
as the other P&R tools expect a specific top-level hierarchy for the design.
The top-level hierarchy must contains the instances of all the I/O pads and
**exactly one** instance of the chip's core model.
|ChipStructure-1|
The designer must provide a configuration file that define the rules for the
placement of the top-level hierarchy (that is, the pads and the core).
This file must be named after the chip's name, by appending ``_chip.py``
(obviously, it is a |Python| file). For instance if the chip netlist file
is called ``amd2901_crl.vst``, then the configuration file must be named
``amd2901_crl_chip.vst``.
Example of chip placement configuration file (for ``AM2901``): ::
chip = \
{ 'pads.south' : [ 'p_a3' , 'p_a2' , 'p_a1' , 'p_r0'
, 'p_vddick0', 'p_vssick0', 'p_a0' , 'p_i6'
, 'p_i8' , 'p_i7' , 'p_r3' ]
, 'pads.east' : [ 'p_zero' , 'p_i0' , 'p_i1' , 'p_i2'
, 'p_vddeck0', 'p_vsseck0', 'p_q3' , 'p_b0'
, 'p_b1' , 'p_b2' , 'p_b3' ]
, 'pads.north' : [ 'p_noe' , 'p_y3' , 'p_y2' , 'p_y1'
, 'p_y0' , 'p_vddeck1', 'p_vsseck1', 'p_np'
, 'p_ovr' , 'p_cout' , 'p_ng' ]
, 'pads.west' : [ 'p_cin' , 'p_i4' , 'p_i5' , 'p_i3'
, 'p_ck' , 'p_d0' , 'p_d1' , 'p_d2'
, 'p_d3' , 'p_q0' , 'p_f3' ]
, 'core.size' : ( 1500, 1500 )
, 'chip.size' : ( 3000, 3000 )
, 'chip.clockTree' : True
}
The file must contain *one dictionnary* named ``chip``.
+----------------------+-------------------------------------------------------+
| Chip Dictionnary |
+----------------------+-------------------------------------------------------+
| Parameter Key/Name | Value/Contents type |
+======================+=======================================================+
| ``'pad.south'`` | Ordered list (left to right) of pad instances names |
| | to put on the south side of the chip |
+----------------------+-------------------------------------------------------+
| ``'pad.east'`` | Ordered list (down to up) of pad instances names |
| | to put on the east side of the chip |
+----------------------+-------------------------------------------------------+
| ``'pad.north'`` | Ordered list (left to right) of pad instances names |
| | to put on the north side of the chip |
+----------------------+-------------------------------------------------------+
| ``'pad.west'`` | Ordered list (down to up) of pad instances names |
| | to put on the west side of the chip |
+----------------------+-------------------------------------------------------+
| ``'core.size'`` | The size of the core (to be used by the placer) |
+----------------------+-------------------------------------------------------+
| ``'chip.size'`` | The size of the whole chip. The sides must be great |
| | enough to accomodate all the pads |
+----------------------+-------------------------------------------------------+
| ``'chip.clockTree'`` | Whether to generate a clock tree or not. This calls |
| | the ClockTree plugin |
+----------------------+-------------------------------------------------------+
Configuration parameters, defaults are defined in ``etc/coriolis2/<STECHNO>/plugins.conf``.
+-----------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+===================================+==================+============================+
| **Chip Plugin Parameters** |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.count`` | TypeInt | :cb:`5` |
| +------------------+----------------------------+
| | The minimum number of rails around the core |
| | block. Must be odd and suppérior to 5. |
| | One rail for the clock and at least two pairs |
| | of power/grounds |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.hWidth`` | TypeInt | :cb:`12` |
| +------------------+----------------------------+
| | The horizontal with of the rails |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.vWidth`` | TypeInt | :cb:`12` |
| +------------------+----------------------------+
| | The vertical with of the rails |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.hSpacing`` | TypeInt | :cb:`6` |
| +------------------+----------------------------+
| | The spacing, *edge to edge* of two adjacent |
| | horizontal rails |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.vSpacing`` | TypeInt | :cb:`6` |
| +------------------+----------------------------+
| | The spacing, *edge to edge* of two adjacent |
| | vertical rails |
+-----------------------------------+------------------+----------------------------+
|``chip.pad.pck`` | TypeString | :cb:`pck_px` |
| +------------------+----------------------------+
| | The model name of the pad connected to the |
| | chip external clock |
+-----------------------------------+------------------+----------------------------+
|``chip.pad.pvddeck`` | TypeString | :cb:`pvddeck_px` |
| +------------------+----------------------------+
| | The model name of the pad connected to the |
| | ``vdde`` (external power) and suppling it to |
| | the core |
+-----------------------------------+------------------+----------------------------+
|``chip.pad.pvsseck`` | TypeString | :cb:`pvsseck_px` |
| +------------------+----------------------------+
| | The model name of the pad connected to the |
| | ``vsse`` (external ground) and suppling it to |
| | the core |
+-----------------------------------+------------------+----------------------------+
|``chip.pad.pvddick`` | TypeString | :cb:`pvddick_px` |
| +------------------+----------------------------+
| | The model name of the pad connected to the |
| | ``vddi`` (internal power) and suppling it to |
| | the core |
+-----------------------------------+------------------+----------------------------+
|``chip.pad.pvssick`` | TypeString | :cb:`pvssick_px` |
| +------------------+----------------------------+
| | The model name of the pad connected to the |
| | ``vssi`` (internal ground) and suppling it to |
| | the core |
+-----------------------------------+------------------+----------------------------+
.. note::
If no clock tree is generated, then the clock rail is *not* created.
So even if the requested number of rails ``chip.block.rails.count`` is, say 5,
only four rails (2* ``power``, 2* ``ground``) will be generateds.
Clock Tree
~~~~~~~~~~
Insert a clock tree into a block. The clock tree uses the H strategy.
The clock net is splitted into sub-nets, one for each branch of the
tree.
* On **chips** design, the sub-nets are createds in the model of the
core block (then trans-hierarchically flattened to be shown at
chip level).
* On **blocks**, the sub nets are created directly in the top block.
* The sub-nets are named according to a simple geometrical scheme.
A common prefix ``ck_htree``, then one postfix by level telling
on which quarter of plane the sub-clock is located:
#. ``_bl``: bottom left plane quarter.
#. ``_br``: bottom right plane quarter.
#. ``_tl``: top left plane quarter.
#. ``_tr``: top right plane quarter.
We can have ``ck_htree_bl``, ``ck_htree_bl_bl``, ``ch_htree_bl_tl`` and so on.
The clock tree plugin works in four steps:
#. Build the clock tree: creates the top-block abutment box, compute the
levels of H tree neededs and place the clock buffers.
#. Once the clock buffers are placed, calls the placer (|etesian|) to place
the ordinary standart cells, whithout disturbing clock H-tree buffers.
#. At this point we know the exact positions of all the DFFs, so we can
connect them to the nearest H-tree leaf clock signal.
#. Leaf clock signals that are not connecteds to any DFFs are removed.
Netlist reorganisation:
* Obviously the top block or chip core model netlist is modificated to
contains all the clock sub-nets. The interface is *not* changed.
* If the top block contains instances of other models *and* those models
contains DFFs that get re-connecteds to the clock sub-nets (from the
top level). Change both the model netlist and interface to propagate
the relevant clock sub-nets to the instanciated model. The new model
with the added clock signal is renamed with a ``_clocked`` suffix.
For example, the sub-block model ``ram.vst`` will become ``ram_clocked.vst``.
.. note::
If you are to re-run the clock tree plugin on a netlist, be careful
to erase any previously generated ``_clocked`` file (both netlist and
layout: ``rm *.clocked.{ap,vst}``). And restart |cgt| to clear it's
memory cache.
Configuration parameters, defaults are defined in ``etc/coriolis2/<STECHNO>/plugins.conf``.
+-----------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+===================================+==================+============================+
| **ClockTree Plugin Parameters** |
+-----------------------------------+------------------+----------------------------+
|``clockTree.minimumSide`` | TypeInt | :cb:`300` |
| +------------------+----------------------------+
| | The minimum size below which the clock tree |
| | will stop to perform quadri-partitions |
+-----------------------------------+------------------+----------------------------+
|``clockTree.buffer`` | TypeString | :cb:`buf_x2` |
| +------------------+----------------------------+
| | The buffer model to use to drive sub-nets |
+-----------------------------------+------------------+----------------------------+
|``clockTree.placerEngine`` | TypeString | :cb:`Etesian` |
| +------------------+----------------------------+
| | The placer to use. Other value is ``Mauka`` |
| | the simulated annealing placer which will go |
| | into retirement very soon |
+-----------------------------------+------------------+----------------------------+
Recursive-Save (RSave)
~~~~~~~~~~~~~~~~~~~~~~
Perform a recursive top down save of all the models from the top cell
loaded in |cgt|. Force a write of any non-terminal model. This plugin is used
by the clock tree plugin after the netlist clock sub-nets creation.
A Simple Example: AM2901
========================
To illustrate the capabilities of |Coriolis| tools and |Python| scripting, a small
example, derived from the |Alliance| :cb:`AM2901` is supplied.
This example contains only the synthetized netlists and the :cb:`design.py` script
which perform the whole P&R of the design. Just lanch |cgt| then execute :cb:`design.py`.
This example contains only the synthetized netlists and the :cb:`doChip.py` script
which perform the whole P&R of the design.
You can generate the chip using one of the following method:
#. **Command line mode:** directly run the script: ::
dummy@lepka:AM2901$ ./doChip -V --cell=amd2901
#. **Graphic mode:** launch |cgt|, load chip netlist ``amd2901`` (the top cell)
then run the |Python| script :cb:`doChip.py`.
.. note::
Between two consecutive run, be sure to erase the netlist/layout generateds: ::
dummy@lepka:AM2901$ rm *_clocked*.vst *.ap

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@ -1,11 +1,12 @@
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% Polyline
45.000 slw
n 1800 5700 m
2100 5700 l gs col0 s gr
% Polyline
15.000 slw
[360] 0 sd
n 2025 2025 m 4875 2025 l 4875 4875 l 2025 4875 l
cp gs col12 s gr [] 0 sd
% Polyline
n 1800 6600 m
2100 6600 l gs col12 s gr
% Polyline
45.000 slw
n -2400 3150 m -5775 3150 l -5775 2175 l -5325 1725 l 975 1725 l 975 3150 l
-2400 3150 l cp gs col0 s gr
% Polyline
n -3000 1725 m -3000 2025 l -1800 2025 l
-1800 1725 l gs col0 s gr
% Polyline
15.000 slw
gs clippath
-4840 2296 m -5124 2343 l -5104 2461 l -4820 2414 l -4820 2414 l -5067 2395 l -4840 2296 l cp
eoclip
n -2850 2025 m
-5100 2400 l gs col0 s gr gr
% arrowhead
n -4840 2296 m -5067 2395 l -4820 2414 l -4840 2296 l cp gs col7 1.00 shd ef gr col0 s
% Polyline
gs clippath
-3082 2225 m -3340 2353 l -3286 2460 l -3028 2332 l -3028 2332 l -3270 2386 l -3082 2225 l cp
eoclip
n -2550 2025 m
-3300 2400 l gs col0 s gr gr
% arrowhead
n -3082 2225 m -3270 2386 l -3028 2332 l -3082 2225 l cp gs col7 1.00 shd ef gr col0 s
% Polyline
gs clippath
-1769 2332 m -1513 2460 l -1459 2353 l -1715 2225 l -1715 2225 l -1528 2386 l -1769 2332 l cp
eoclip
n -2250 2025 m
-1500 2400 l gs col0 s gr gr
% arrowhead
n -1769 2332 m -1528 2386 l -1715 2225 l -1769 2332 l cp gs col7 1.00 shd ef gr col0 s
% Polyline
gs clippath
21 2414 m 304 2461 l 324 2343 l 41 2296 l 41 2296 l 268 2395 l 21 2414 l cp
eoclip
n -1950 2025 m
300 2400 l gs col0 s gr gr
% arrowhead
n 21 2414 m 268 2395 l 41 2296 l 21 2414 l cp gs col7 1.00 shd ef gr col0 s
% Polyline
n -5700 2400 m -4500 2400 l -4500 3000 l -5700 3000 l
cp gs col0 s gr
% Polyline
gs clippath
-5159 3628 m -5160 3915 l -5040 3915 l -5039 3628 l -5039 3628 l -5099 3868 l -5159 3628 l cp
eoclip
n -5100 3000 m
-5100 3900 l gs col0 s gr gr
% arrowhead
n -5159 3628 m -5099 3868 l -5039 3628 l -5159 3628 l cp gs 0.00 setgray ef gr col0 s
% Polyline
n -3900 2400 m -2700 2400 l -2700 3000 l -3900 3000 l
cp gs col0 s gr
% Polyline
gs clippath
-3359 3628 m -3360 3915 l -3240 3915 l -3239 3628 l -3239 3628 l -3299 3868 l -3359 3628 l cp
eoclip
n -3300 3000 m
-3300 3900 l gs col0 s gr gr
% arrowhead
n -3359 3628 m -3299 3868 l -3239 3628 l -3359 3628 l cp gs 0.00 setgray ef gr col0 s
% Polyline
n -2100 2400 m -900 2400 l -900 3000 l -2100 3000 l
cp gs col0 s gr
% Polyline
gs clippath
-1559 3628 m -1560 3915 l -1440 3915 l -1439 3628 l -1439 3628 l -1499 3868 l -1559 3628 l cp
eoclip
n -1500 3000 m
-1500 3900 l gs col0 s gr gr
% arrowhead
n -1559 3628 m -1499 3868 l -1439 3628 l -1559 3628 l cp gs 0.00 setgray ef gr col0 s
% Polyline
n -300 2400 m 900 2400 l 900 3000 l -300 3000 l
cp gs col0 s gr
% Polyline
gs clippath
240 3628 m 240 3915 l 360 3915 l 360 3628 l 360 3628 l 300 3868 l 240 3628 l cp
eoclip
n 300 3000 m
300 3900 l gs col0 s gr gr
% arrowhead
n 240 3628 m 300 3868 l 360 3628 l 240 3628 l cp gs 0.00 setgray ef gr col0 s
/Helvetica-Bold ff 233.33 scf sf
2400 5700 m
gs 1 -1 sc (coeur) col0 sh gr
/Helvetica ff 233.33 scf sf
2400 6000 m
gs 1 -1 sc (ialu) col0 sh gr
/Helvetica ff 233.33 scf sf
2400 6300 m
gs 1 -1 sc (iaccu) col0 sh gr
/Helvetica ff 233.33 scf sf
2400 6600 m
gs 1 -1 sc (iram) col0 sh gr
/Helvetica-Bold ff 233.33 scf sf
-2400 1950 m
gs 1 -1 sc (coeur) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
-5100 2625 m
gs 1 -1 sc (ialu) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
-5100 2925 m
gs 1 -1 sc (\(0,0,ID\)) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
-3300 2625 m
gs 1 -1 sc (iaccu) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
-3300 2925 m
gs 1 -1 sc (\(0,0,ID\)) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
-1500 2625 m
gs 1 -1 sc (iram) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
-1500 2925 m
gs 1 -1 sc (\(0,0,ID\)) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
300 2625 m
gs 1 -1 sc (imuxs) dup sw pop 2 div neg 0 rm col0 sh gr
/Helvetica ff 233.33 scf sf
300 2925 m
gs 1 -1 sc (\(0,0,ID\)) dup sw pop 2 div neg 0 rm col0 sh gr
% here ends figure;
pagefooter
showpage
%%Trailer
%EOF

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@ -0,0 +1,148 @@
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After

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@ -78,7 +78,7 @@
\renewcommand{\sectionmark}[1]{\markboth{\thesection\ #1}{\thesection\ #1}}
\renewcommand{\subsectionmark}[1]{}
\lhead[]{Documentation \SoC}
\rhead[]{March 2014}
\rhead[]{March 2015}
\lfoot[]{\UPMC/\LIP/\SoC}
\rfoot[]{\thepage}
\cfoot[]{}

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@ -0,0 +1,4 @@
from Hurricane import DebugSession
#DebugSession.addToTrace( kite.getCell().getNet( 'f_i(3)' ) )

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@ -0,0 +1,31 @@
# -*- Mode:Python -*-
defaultStyle = 'Alliance.Classic [black]'
parametersTable = \
( ('misc.catchCore' , TypeBool , False )
, ('misc.info' , TypeBool , False )
, ('misc.paranoid' , TypeBool , False )
, ('misc.bug' , TypeBool , False )
, ('misc.logMode' , TypeBool , False )
, ('misc.verboseLevel1' , TypeBool , False )
, ('misc.verboseLevel2' , TypeBool , True )
, ('misc.traceLevel' , TypeInt , 1000 )
, ('etesian.spaceMargin' , TypePercentage, 5.0 )
, ('etesian.aspectRatio' , TypePercentage, 100.0 )
# Kite parameters.
, ("kite.eventsLimit" , TypeInt , 1000000 )
, ('katabatic.topRoutingLayer', TypeString , 'METAL5')
, ("kite.hTracksReservedLocal", TypeInt , 4 )
, ("kite.vTracksReservedLocal", TypeInt , 3 )
)
#import os
#
#print ' o Cleaning up ClockTree previous run.'
#for fileName in os.listdir('.'):
# if fileName.endswith('.ap') or (fileName.find('_clocked.') >= 0):
# print ' - <%s>' % fileName
# os.unlink(fileName)

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@ -0,0 +1,2 @@
symbolicTechno = 'cmos'
realTechno = 'hcmos9'

View File

@ -8,6 +8,10 @@
muxe.vst
muxs.vst
ram.vst
design.py
DESTINATION ${examplesInstallDir}/AM2901 )
amd2901_chip.py DESTINATION ${examplesInstallDir}/AM2901 )
install ( FILES doChip.py PERMISSIONS OWNER_EXECUTE GROUP_EXECUTE WORLD_EXECUTE
OWNER_READ GROUP_READ WORLD_READ
OWNER_WRITE
DESTINATION ${examplesInstallDir}/AM2901 )
install ( DIRECTORY .coriolis2 DESTINATION ${examplesInstallDir}/AM2901 )

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@ -0,0 +1,12 @@
#!/usr/bin/env python
chip = { 'pads.south' : [ 'p_a3' , 'p_a2', 'p_a1', 'p_r0', 'p_vddick0', 'p_vssick0', 'p_a0' , 'p_i6', 'p_i8' , 'p_i7' , 'p_r3' ]
, 'pads.east' : [ 'p_zero', 'p_i0', 'p_i1', 'p_i2', 'p_vddeck0', 'p_vsseck0', 'p_q3' , 'p_b0', 'p_b1' , 'p_b2' , 'p_b3' ]
, 'pads.north' : [ 'p_noe' , 'p_y3', 'p_y2', 'p_y1', 'p_y0' , 'p_vddeck1', 'p_vsseck1', 'p_np', 'p_ovr', 'p_cout', 'p_ng' ]
#, 'pads.west' : [ 'p_i5', 'p_i3', 'p_ck' , 'p_d0' , 'p_d1' , 'p_d2', 'p_d3' , 'p_q0' , 'p_f3' ]
, 'pads.west' : [ 'p_cin' , 'p_i4', 'p_i5', 'p_i3', 'p_ck' , 'p_d0' , 'p_d1' , 'p_d2', 'p_d3' , 'p_q0' , 'p_f3' ]
, 'core.size' : ( 1500, 1500 )
, 'chip.size' : ( 3000, 3000 )
, 'chip.clockTree' : True
}

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@ -1,246 +0,0 @@
#!/usr/bin/env python
try:
import sys
import traceback
import os.path
import optparse
import Cfg
import Hurricane
from Hurricane import DbU
from Hurricane import UpdateSession
from Hurricane import Breakpoint
from Hurricane import Transformation
from Hurricane import Instance
import Viewer
import CRL
from helpers import ErrorMessage
import Nimbus
import Metis
import Mauka
import Katabatic
import Kite
import Unicorn
import placeandroute
except ImportError, e:
serror = str(e)
if serror.startswith('No module named'):
module = serror.split()[-1]
print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module
print ' Please check the integrity of the <coriolis> package.'
if str(e).find('cannot open shared object file'):
library = serror.split(':')[0]
print '[ERROR] The <%s> shared library cannot be loaded.' % library
print ' Under RHEL 6, you must be under devtoolset-2.'
print ' (scl enable devtoolset-2 bash)'
sys.exit(1)
except Exception, e:
print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python'
print ' modules. Something may be wrong at Python/C API level.\n'
print ' %s' % e
sys.exit(2)
# Check that all the instances have been placed by Mauka.
def checkForUnplaceds ( cell ):
unplaceds = []
for instance in cell.getInstances():
if instance.getPlacementStatus() == Instance.PlacementStatus.UNPLACED:
unplaceds += [ instance ]
if unplaceds:
message = [ 'Some instances are still unplaceds:' ]
for instance in unplaceds:
message += [ '<%s> of model <%s>'%(str(instance.getName())
,str(instance.getMasterCell().getName())) ]
raise ErrorMessage( 3, message )
return
# Small wrapper to display breakpoints, when in graphic mode only.
def breakpoint ( editor, level, message ):
if editor:
editor.fit()
editor.refresh()
Breakpoint.stop( level, message )
return
def ScriptMain ( cell=None ):
# Force removal of any previouly generated placement (.ap files)
# as they would prevent the the placer to run again.
# This is a little bit inconvenient, but will change in the future.
print ' o Cleaning up any previous run.'
for fileName in os.listdir('.'):
if fileName.endswith('.ap'):
print ' - <%s>' % fileName
os.unlink(fileName)
editor = None
if globals().has_key('__editor'):
print ' o Editor detected, running in graphic mode.'
editor = __editor
Cfg.Configuration.pushDefaultPriority(Cfg.Parameter.Priority.CommandLine)
Cfg.getParamBool('misc.verboseLevel1').setBool(True)
Cfg.getParamBool('misc.verboseLevel2').setBool(True)
Cfg.Configuration.popDefaultPriority()
errorCode = 0
framework = CRL.AllianceFramework.get()
padHeight = DbU.fromLambda( 400.0)
padWidth = DbU.fromLambda( 200.0)
coreSide = DbU.fromLambda(1400.0)
# Cell must be loaded *before* opening the UpdateSession.
print ' o Placing <coeur>.'
modelCoeur = framework.getCell('coeur',CRL.Catalog.State.Logical)
UpdateSession.open()
try:
modelCoeur.setAbutmentBox( Hurricane.Box( DbU.fromLambda(0)
, DbU.fromLambda(0)
, coreSide
, coreSide
) )
# Cannot place a rail if at least one instance is placed.
# (to compute the orientation of the cells rows)
#placeandroute.pyAlimVerticalRail( modelCoeur, coreSide/DbU.fromLambda(5.0*2) )
except Exception, e:
print e; errorCode = 1
# For the geometrical modifications to be taken into account, we must
# close this UpdateSession now. So the chip will see the core correctly.
UpdateSession.close()
if errorCode: sys.exit(errorCode)
print ' o Placing <chip>.'
amd2901 = framework.getCell('amd2901',CRL.Catalog.State.Logical)
if editor: editor.setCell(amd2901)
UpdateSession.open()
try:
chipSide = 11*padWidth + 2*padHeight # Le chip est carre, avec 11 plots par face.
abutmentBoxChip = Hurricane.Box( DbU.fromLambda(0.0)
, DbU.fromLambda(0.0)
, chipSide
, chipSide
)
amd2901.setAbutmentBox( abutmentBoxChip )
instanceCoeur = amd2901.getInstance( 'core' )
instanceCoeur.setTransformation(Hurricane.Transformation( (chipSide-coreSide)/2
, (chipSide-coreSide)/2
, Transformation.Orientation.ID ) )
instanceCoeur.setPlacementStatus( Instance.PlacementStatus.PLACED )
# Placing Pads
southPads = [ 'p_a3' , 'p_a2', 'p_a1', 'p_r0', 'p_vddick0', 'p_vssick0', 'p_a0' , 'p_i6', 'p_i8' , 'p_i7' , 'p_r3' ]
eastPads = [ 'p_zero', 'p_i0', 'p_i1', 'p_i2', 'p_vddeck0', 'p_vsseck0', 'p_q3' , 'p_b0', 'p_b1' , 'p_b2' , 'p_b3' ]
northPads = [ 'p_noe' , 'p_y3', 'p_y2', 'p_y1', 'p_y0' , 'p_vddeck1', 'p_vsseck1', 'p_np', 'p_ovr', 'p_cout', 'p_ng' ]
westPads = [ 'p_cin' , 'p_i4', 'p_i5', 'p_i3', 'p_ck' , 'p_d0' , 'p_d1' , 'p_d2', 'p_d3' , 'p_q0' , 'p_f3' ]
for (key,listPads) in {'south':southPads, 'east':eastPads, 'north':northPads, 'west':westPads}.iteritems():
print ' o Pads on %s side:' %key
for ipad in range(len(listPads)):
pad = amd2901.getInstance( listPads[ipad] )
print ' - Placing pad: <%s> (model:<%s>).' % (listPads[ipad],str(pad.getMasterCell().getName()))
# south
if key == 'south' :
xpad = abutmentBoxChip.getXMin() + padHeight + ipad*(padWidth)
ypad = abutmentBoxChip.getYMin() + padHeight
pad.setTransformation( Hurricane.Transformation( xpad, ypad, Transformation.Orientation.MY) )
# east
if key == 'east' :
xpad = abutmentBoxChip.getXMax() - padHeight
ypad = padHeight + padWidth + ipad*(padWidth)
pad.setTransformation( Hurricane.Transformation( xpad, ypad, Transformation.Orientation.R3) )
# north
if key == 'north' :
xpad = padHeight + ipad*(padWidth)
ypad = abutmentBoxChip.getYMax() - padHeight
pad.setTransformation( Hurricane.Transformation( xpad, ypad, Transformation.Orientation.ID) )
# west
if key == 'west' :
xpad = padHeight
ypad = padHeight + ipad*(padWidth)
pad.setTransformation( Hurricane.Transformation( xpad, ypad, Transformation.Orientation.R1) )
pad.setPlacementStatus( Instance.PlacementStatus.PLACED )
except ErrorMessage, e:
print e; errorCode = e.code
except Exception, e:
print '\n\n', e; errorCode = 1
traceback.print_tb(sys.exc_info()[2])
UpdateSession.close()
if errorCode: sys.exit(errorCode)
breakpoint( editor, 1, 'Chip After Pad Placement' )
try:
# Now run the tools.
coeur = framework.getCell('coeur',CRL.Catalog.State.Logical)
mauka = Mauka.MaukaEngine.create(coeur)
mauka.run()
mauka.destroy()
breakpoint( editor, 1, 'Core After Standard Cell Placement' )
placeandroute.pyAlimConnectors(coeur)
# This is gross. It's the ghost of Wu Yifei and his demonic code...
# Will not be needed in the future (dynamic detection based on the
# transformations).
for pad in southPads: placeandroute.pad_south += [ amd2901.getInstance(pad) ]
for pad in northPads: placeandroute.pad_north += [ amd2901.getInstance(pad) ]
for pad in eastPads: placeandroute.pad_east += [ amd2901.getInstance(pad) ]
for pad in westPads: placeandroute.pad_west += [ amd2901.getInstance(pad) ]
placeandroute.pyPowerRing( amd2901, amd2901.getInstance('core'), 3 )
placeandroute.pyRouteCk ( amd2901, amd2901.getNet('ckc') )
breakpoint( editor, 1, 'Core After Clock & Power Routing' )
kite = Kite.KiteEngine.create( amd2901 )
kite.runGlobalRouter( Kite.KtBuildGlobalRouting )
kite.loadGlobalRouting( Katabatic.EngineLoadGrByNet, [] )
kite.layerAssign( Katabatic.EngineNoNetLayerAssign )
kite.runNegociate()
breakpoint( editor, 1, 'Routing done, but router still active for inspection.' )
kite.finalizeLayout()
kite.destroy()
# Write back layout to disk if everything has gone fine.
# Must write all the sub-blocks of the core but *not* the
# standard cell (mainly the feed-through).
for instance in modelCoeur.getInstances():
masterCell = instance.getMasterCell()
if not masterCell.isTerminal():
framework.saveCell( masterCell, CRL.Catalog.State.Physical )
framework.saveCell( modelCoeur, CRL.Catalog.State.Physical )
framework.saveCell( amd2901 , CRL.Catalog.State.Physical )
except ErrorMessage, e:
print e; errorCode = e.code
except Exception, e:
print '\n\n', e; errorCode = 1
traceback.print_tb(sys.exc_info()[2])
if editor: editor.setCell(amd2901)
return 0
if __name__ == '__main__':
ScriptMain()
sys.exit(0)

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#!/usr/bin/env python
try:
import sys
import traceback
import os.path
import optparse
import Cfg
import Hurricane
from Hurricane import DbU
from Hurricane import UpdateSession
from Hurricane import Breakpoint
from Hurricane import Transformation
from Hurricane import Instance
import Viewer
import CRL
from helpers import ErrorMessage
import Nimbus
import Metis
import Mauka
import Katabatic
import Kite
import Unicorn
import plugins.ChipPlugin
import plugins.RSavePlugin
except ImportError, e:
serror = str(e)
if serror.startswith('No module named'):
module = serror.split()[-1]
print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module
print ' Please check the integrity of the <coriolis> package.'
sys.exit(1)
if str(e).find('cannot open shared object file'):
library = serror.split(':')[0]
print '[ERROR] The <%s> shared library cannot be loaded.' % library
print ' Under RHEL 6, you must be under devtoolset-2.'
print ' (scl enable devtoolset-2 bash)'
sys.exit(1)
except Exception, e:
print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python'
print ' modules. Something may be wrong at Python/C API level.\n'
print ' %s' % e
sys.exit(2)
DoPlacement = 0x0001
DoRouting = 0x0002
AllStages = DoPlacement|DoRouting
framework = CRL.AllianceFramework.get()
def ScriptMain ( **kw ):
success = False
doStages = AllStages
if kw.has_key('doStages'):
doStages = kw['doStages']
try:
cell, editor = plugins.kwParseMain( **kw )
if doStages & DoPlacement:
success = plugins.ChipPlugin.ScriptMain( **kw )
if not success: return False
if doStages & DoRouting:
routingNets = []
kite = Kite.KiteEngine.create( cell )
#kite.printConfiguration()
kite.runGlobalRouter ( Kite.KtBuildGlobalRouting )
kite.loadGlobalRouting( Katabatic.EngineLoadGrByNet, routingNets )
kite.layerAssign ( Katabatic.EngineNoNetLayerAssign )
kite.runNegociate ()
success = kite.getToolSuccess()
kite.finalizeLayout()
kite.destroy()
cell.setName( cell.getName()+'_kite' )
framework.saveCell( cell, CRL.Catalog.State.Logical )
plugins.RSavePlugin.ScriptMain( **kw )
except Exception, e:
print e
return success
if __name__ == '__main__':
parser = optparse.OptionParser()
parser.add_option( '-c', '--cell' , type='string', dest='cell' , help='The name of the chip to build, whithout extension.')
parser.add_option( '-s', '--script', type='string', dest='script' , help='The name of a Python script, without extension.')
parser.add_option( '-v', '--verbose' , action='store_true', dest='verbose' , help='First level of verbosity.')
parser.add_option( '-V', '--very-verbose' , action='store_true', dest='veryVerbose', help='Second level of verbosity.')
parser.add_option( '-p', '--place' , action='store_true', dest='doPlacement', help='Perform chip placement step only.')
parser.add_option( '-r', '--route' , action='store_true', dest='doRouting' , help='Perform routing step only.')
(options, args) = parser.parse_args()
doStages = 0
if options.verbose: Cfg.getParamBool('misc.verboseLevel1').setBool(True)
if options.veryVerbose: Cfg.getParamBool('misc.verboseLevel2').setBool(True)
if options.doPlacement: doStages |= DoPlacement
if options.doRouting: doStages |= DoRouting
if not doStages: doStages = AllStages
kw = { 'doStages':doStages }
if options.script:
try:
module = __import__( options.script, globals(), locals() )
if not module.__dict__.has_key('ScriptMain'):
print '[ERROR] Script module <%s> do not contains a ScripMain() function.' % options.script
sys.exit(1)
cell = module.__dict__['ScriptMain']( **kw )
kw['cell'] = cell
except ImportError, e:
module = str(e).split()[-1]
print '[ERROR] The <%s> script cannot be loaded.' % module
print ' Please check your design hierarchy.'
sys.exit(1)
except Exception, e:
print '[ERROR] A strange exception occurred while loading the Python'
print ' script <%s>. Please check that module for error:\n' % options.script
traceback.print_tb(sys.exc_info()[2])
print ' %s' % e
sys.exit(2)
elif options.cell:
kw['cell'] = framework.getCell( options.cell, CRL.Catalog.State.Views )
success = ScriptMain( **kw )
shellSuccess = 0
if not success: shellSuccess = 1
sys.exit( shellSuccess )