More talkative VST parser.
* Change: In CRL Core, in VstParserGrammar.yy display in which mode a file is read. Behavioral, structural or model. Model is the step of reading the instance's models before truly reading the file. In addition, a small optimization, when in behavioral mode, parse the file only once.
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@ -1272,11 +1272,17 @@ namespace CRL {
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// -------------------------------------------------------------------
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// Function : "vstParser()".
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//
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// The parser work in 2.5 (two and a half) passes:
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// 1.0 Read the vst in search of COMPONENTS and/or instances declarations.
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// Build an ordered list of all the model (i.e. master Cell) needed.
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// 1.5 Load, in order all the Cell required. This is a recursive process,
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// that is, the model, in turn can trigger the loading of yet other
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// master Cells.
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// 2.0 Read the vst a second time, actually builing the Cell.
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void vstParser ( const string cellPath, Cell *cell )
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{
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cmess2 << " " << tab << "+ " << cellPath << " (childs)" << endl; tab++;
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static bool firstCall = true;
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if ( firstCall ) {
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firstCall = false;
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@ -1299,42 +1305,47 @@ void vstParser ( const string cellPath, Cell *cell )
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IoFile ccell ( cellPath );
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ccell.open ( "r" );
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yyin = ccell.getFile ();
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if ( !firstCall ) yyrestart ( VSTin );
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yyparse ();
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while ( !Vst::states->_cellQueue.empty() ) {
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if ( !Vst::framework->getCell ( getString(Vst::states->_cellQueue.front())
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, Catalog::State::Views
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, Vst::states->_state->getDepth()-1) ) {
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throw Error ( "CParsVst() VHDL Parser:\n"
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" Unable to find cell \"%s\", please check your <.coriolis2/settings.py>.\n"
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, getString(Vst::states->_cellQueue.front()).c_str()
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);
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if (Vst::states->_behavioral) {
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cmess2 << " " << tab << "+ " << cellPath << " [behavioral]" << endl;
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} else {
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cmess2 << " " << tab << "+ " << cellPath << " [models]" << endl; tab++;
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// 1.0 step: Build the ordered list of model (Cell) required by the instances.
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yyin = ccell.getFile ();
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if ( !firstCall ) yyrestart ( VSTin );
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yyparse ();
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// 1.5 step: Load, in order, the model Cells (recursive).
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while ( !Vst::states->_cellQueue.empty() ) {
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if ( !Vst::framework->getCell ( getString(Vst::states->_cellQueue.front())
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, Catalog::State::Views
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, Vst::states->_state->getDepth()-1) ) {
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throw Error ( "CParsVst() VHDL Parser:\n"
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" Unable to find cell \"%s\", please check your <.coriolis2/settings.py>.\n"
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, getString(Vst::states->_cellQueue.front()).c_str()
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);
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}
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Vst::states->_cellQueue.pop_front();
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}
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Vst::states->_cellQueue.pop_front();
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--tab;
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cmess2 << " " << tab << "+ " << cellPath << " [structural]" << endl;
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}
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cmess2 << " " << --tab << "+ " << cellPath << " (loading)" << endl;
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Vst::states->_firstPass = false;
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Vst::states->_vhdLineNumber = 1;
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ccell.close ();
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// 2.0 step: Now really read and build the Cell.
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ccell.open ( "r" );
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yyin = ccell.getFile ();
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yyrestart ( VSTin );
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UpdateSession::open ();
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yyparse ();
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UpdateSession::close ();
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forEach ( Net*, inet, Vst::states->_cell->getNets() ) {
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cerr << *inet << endl;
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}
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Vst::ClearIdentifiers ();
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Vst::states.pop_back();
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ccell.close ();
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}
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