* Bug: In AutoSegment::getEndAxes(), as the NonAligned flag may be
wrong, always loop over the aligneds (if any). Then, the
target axis computation was wrong, using a min() instead of
a max().
This was, in turn, wrongly activating isNearMinArea() and
causing non-minimal length segment to have their extremeties
extented. And, in the end, Track overlap.
This was the reason why we, sometimes got "UNCONNECTED" errors in the
VHDL PORT MAP statements. This was the remnants of the originally
connected driver.
* Bug: In Etesian::BufferTree, as the root driver is disconnected from
all the sinks, but the top tree buffer, we may end up with
unconnected signal on instances that were using it.
So now, call BufferTree::rcleaupNet() to remove the Net in
the Cell that where used to "transmit" the original driver.
* Bug: In Etesian::BufferTree, no longer use a _isDeepNet attribute
guessed from the occurrences pathes of the RoutingPad, but
trust the Net::isDeepNet() method.
* New: In Katana::DataNegociate, add a "sameRipup" counter to keep
the *consecutive* number of time a segment is put in the same
track.
* New: In TrackSegment::setAxis(), update/reset the "sameRipup"
counter of the DataNegociate.
* New: In TrackCost, add new flag "Blacklisted" to mark Tracks that
have been riped up too much in a consecutive row.
TrackCost::Compare::operator() will then sort the blacklisted
track after the non-blacklisted ones.
* New: In SegmentFsm CTOR, raise the Blacklist flag on the TrackCost
if the "sameRipup" is above 10. This to get away from a state
well in the ripup.
Bug: In NetBuilderHV::doRp_AutoContact(), when encountering a
punctual RoutingPad in METAL1, create the protection in the
METAL2 layer instead of METAL1 (current layer).
* Bug: In NetBuilder::setStartHook(), trigger the "move up" of
global routing only when encountering RoutingPad of a macro
block and *not* an I/O pin of the whole block (at the edge).
Boils down to look if the RoutingPad is anchored on a Pin
or a Segment (macro block).
* Bug: In cumulus/plugins/rsave.py, the Cells where saveds each time
one instance of was encountered. Resulting in multiple saves.
It was, of course, ineficient, but it also triggers a bug
that seems to happen after multiple save : the VHDL additional
property was deleted *before* the full hierarchical dump was
finished.
Now, we save each Cell only once so it does not occur, but
should make a deeper investigation later.
* Change: In AutoHorizontal::setDuSource() & ::setDuTarget() (& AutoVertical),
check that the requested "du" is less than a pitch (this is not an
upper bound). Issue a warning if not true.
* Change: In AutoSegment::revalidate(), when passing the previous span
interval to expandToMinLength(), if we are in creation stage, make
it empty because it has no sense yet and can lead to a lock in a
too narrow span.
Change the coupled behavior of expandToMinLength() vs.
unexpandToMinLength(), the call to "unexpand" will be done on
AutoSegments that are flagged with SegAtMinArea, instead of
using the return value of "expand". This way we control across
multiple revalidate() if a segment can be "unexpanded".
* Bug: In AutoSegment::expandToMinLength(), not only try to shift left
if we are beyoond the max bound but also to the right if we are
below the min bound.
the span on the target and source were miscalculated, we must
add the half-minimal distance to get the span inside the Track.
* Change: In AutoSegment::isMiddleStack(), rename into isNearMinArea()
as we check for any *small length* set of AutoSegments and not
only the one part of a middle stack. In some rare instances,
two aligned segments can nevertheless be too short.
* Bug: In AutoSegment::reduceDoglegLayer(), when finding a reduced
segment also reset it's duSource & duTarget because it will
no longer be an isolated strip of metal.
* Change: In AutoHorizontal::updateOrient(), when there is a
source/target swap, no need to exchange the dxSource and
dxTarget extentions.
* Change: In AutoHorizontal::setDuSource() & ::setDuTarget(), check
for du bigger than the pitch, which should never occur and
display a warning.
Same modification in AutoVertical.
* Change: In Track::repair(), now invalidate the shifted segments
to ensure cache coherency with the TrackElement.
Do not take AutoSegment in non-preferred direction into
account, and especially do not try to resize them.
Now, invalidate the corrected segments (see below).
* Change: In KatanaEngine::finalizeLayout(), move the track repair
stage from here into NegociateWidow::run(). This way we avoid
the false warning about segment overlap in the data-base final
check. The false warning was because the AutoSegment where
shifted but not invalidated/revalidated leading to a cache
incoherency in the TrackElement. Now they *are* invalidated
and updated.
* Bug: In Track::checkMinArea(), do not check for minimal area when
a segment is overlapping a same net neighbor. To avoid false
minimum area violation warnings.
* Bug: In AutoContactTurn::updateTopology(), in some case we were making
doglegs on segments in non-preferred routing direction (mostly M2).
This must be never be done. As, by construction, at least one segment
of the turn must be in the preferred routing direction, always use
this one to make the dogleg.
This bug is likely to explain the remaining "bad spin" in the
final self-check of the routing data-structure.
The decoupling of the cell gauge and the routing gauge implies that
the METAL2 & METAL3 terminals of macro blocks cannot be aligned on
the routing tracks anymore. That is, an horizontal METAL2 terminal
will not be on a track axis, but offgrid, so we no longer can use
a METAL2 horizontal segment to connect to it. Making an adjustement
between the offgrid terminal and the on-grid segment has proven
too complex and generating difficult configuration for the router.
Moreover, METLA2 terminal could be fully inside a METAL2 blockage.
So now, when the gauges are decoupled, we connect the METAL2 and
METAL3 the same way we do for METAL1: *from above* in the perpandicular
direction and using a *sliding* VIA. We assume that those kind of
terminals in upper metals are quite long.
* New: In Hurricane::Rectilinear, export the isNonRectangle() method
to the Python interface.
* New: In CRL::RoutingGauge, add function isSuperPitched() with the
associated boolean attribute. Set to true when each pitch of
each layer is independant (not low fractional multiples).
* New: In AnabaticEngine, add the ability to temporarily disable the
canonize() operation (mainly used in dogleg creation).
* New: In AutoSegment::canonize(), do nothing if the operation is
disabled by AnabaticEngine.
* Bug: In Session::_revalidateTopology(), disable the canonization
during the topology updating of a net. Too early canonization
was occuring in makeDogleg() leading to incoherencies when
performing the later canonization stage over the complete net.
Mostly occured in the initial build stage of the net.
* New: In GCell, add function postGlobalAnnotate(), if a layer
is fully blocked (above 0.9), typically, under a blockage,
add a further capacity decrease of 2 on the edges. So we may
handle a modicum of doglegs.
* Bug; In GCell::addBlockage(), removeContact(), removeHSegment()
and removeVSegment(), forgot to set the Invalidated flag.
This may have lead to innacurate densities.
* Change: In GCell::updateDensity(), more complex setting of the
GoStraight flag. This flag is now set if we don't have two
*contiguous* below 60% of density. We need free contiguous
layers to make doglegs.
* New: In NetBuilder, now manage a current state flag along
with the state flag of the *source* GCell. This flag is used
to tell if the GCell needs it's *global* routing to be done
using the upper layers (METAL4 & METAL5) instead of the
lower ones.
* New: In NetBuilder::setStartHook(), set the state flag of the
GCell to ToUpperRouting when processing a global routing
articulation and one of the base layer is obstructed
above 0.9.
In GCell with terminals, also set ToUpperRouting when there
are some in METAL2 / METAL3 and the gauge is not super-pitched.
* New: In NetBuilder, function isInsideBlockage(), to check if a
terminal is completely or partially enclosed in a blockage.
* Change: In NetBuilderHV::doRp_AutoContact(), remove support for
trying to put on grid misaligned METAL2/METAL3.
Instead systematically access them from above.
Do not cover with fixed protection terminals that are already
enclosed in blockages.
* Bug: In NetBuilderHV::doRp_AutoContact(), always add the terminal
contact in the requested GCell and not the target/source one,
in case the terminal span several GCells.
* Change: In NetBuilderHV::doRp_Access(), create the local wiring
according to the RoutingPad layer.
* Change: In NetBuilderHV::_do_xG(), _do_2G(),
create the global wiring in upper layers, according to the
ToUpperRouting flag.
* Change: In NetBuilderHV::_do_xG_xM3(), now delegate to
_do_xG_xM3_baseRouting() and _do_xG_xM3_upperRouting() if the
density at terminal level is above 0.5.
* New: NetBuilderHV::_do_xG_xM3_baseRouting() and
_do_xG_xM3_upperRouting() separated function to manage the
local routing.
* Change: In NetBuilder::_do_globalSegment(), if the currently
processed GCell or it's source is in ToUpperRouting mode,
move up the global segment. Do *not* use the moveUp() function
which would create doglegs unwanted at this stage.
* New: In KatanaEngine::annotateGlobalGraph(), call postGlobalAnnotate()
on the GCell after the blockages have been taken into accound to
add the penalty.
* Bug: In Track::getPrevious(), correctly manage the 0 value for the
index argument. Strange it didn't show earlier.
Same goes for Track::expandFreeInterval().
After a Cell has been created in memory (by parsers or Python scripts)
we can annotate it with the Spice parser so it will know the right
order with which to create the subcircuit call ('x').
* New: In CRL::Spice::load(), add support to read the ".subckt" card
and guess the right ordering for generating the 'x' (subcircuit
card call).
* Bug: In Spice::SpiceBit & Spice::BitExtension, when a Net bit property
is removed, if it's the currently cached property in BitExtension
it may lead to a crash. So when a property is destroyed, we must
also clear the cache (see remove(), clearCache() & onReleasedby()).
I'm wary that this could also happen on other kind of cached
extensions...
* New: In CRL::NamingScheme, new method vhdlToVlog() to translate back
VHDL net name into Verilog. Currently only changes "()" into "[]".
Used to generate the commented SPICE interface for Alliance compliance.
* Change: In Spice::Entity, previously all the ordering where removed
between each run of the SPICE parser, but the orders read from
SPICE file (mostly standard cells) must be kept. So add a flag
ReferenceCell to prevent the removal by ::destroyAll().
* Bug: In NetlistModel::setCell() template, forgot to send the
"layoutAboutToBeChanged" signal before disconnecting the
netlist datas. This seemed to go unnoticed until ported
under Qt5. Was generating strange random core dump when
running the engines with a net kept selected. Disgraceful
crash during demos...
* Bug: In Selector::_preDestroy(), *do not* iterate over the _cellWidgets
map as we destroy it's elements! We end up in destroyed ones...
Instead destroy the first one until the map is empty.
* Change: In CellWidget::_redraw(), the boundaries, that is, instances
abutment boxes where drawn *after* everything else, so they where
hiding more interesting informations (especially at low zoom level)
like routing wires.
Now draw them *first* so they are *below*.
* Change: In CellImage::setScreenCellWidget, fully copy the display
settings from the reference widget (not just part of them).
* Bug: In CellImage::toImage(), if the abutment box of the displayed
cell is not *fully* includer in the viewer area, do *not* try to
reframe it. The reframe() method seems to be buggy, works OK
just without calling it.
* Change: In unicorn/python/unicornInit.py, when iterating over all the
loaded modules, now we have "namespace" that have a __file__
attribute which is set to None. Skip them.
* Change: In stratus1/st_net.py, "is" must be replaced by "==" when
doing string comparison.
* Change: In stratus1/st_parser.py, open file in "rb" mode instead
of "r" (so we get a bytestream as now required by Python).
* Bug: In Viewer::SelectionPopup(), the window attribute
Qt::WA_DeleteOnClose was *not* cleared. So the window was deleted
after first use while it was though staying allocated.
Again, generating weird crashes.
Took the occasion to slightly redesign the behavior to select
and highlight individual components.
* Bug: In Isobar3::PyTypeManager, the accessors _getCppTypeName() and
_getPyTypeName() where returning string *by value*, hence, short
lived copies.
But, in _setupPyType() and _addToModule(), as we interface with
the Python/C API, we extract the c_str(). Which where removed as
we used temporary objects. Leading to memory corruption and weird
crashes.
Now returns "const string&" so the c_str() stays allocated.
* Bug: In CellWidget::DrawingQuery::drawGo(), the display condition was
wrong, it was requiring *both* width & height to be above the display
threshold. Either one is sufficient to activate the display.
Was causing the selective diseapearance of gates at low zoom level
and printed version.
* Change: In CellPrinter, force the display threshold to one pixel in it's
internal CellWidget used for printing.
* Bug: In Katana::DataNegociate::update(), when computing the length of
source & target extension on a perpandicular segment, must use the
extensions of the *directly* connected AutoSegment (the baseSegment)
and not the canonical one that may be different, so with unrelated
extensions.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), the RoutingPads
for the input and output of the buffer where sometimes put too
close from each others, giving the pitch of the vertical tracks.
Now shift one pitch left the vertical branchs of the H-Tree.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), also shift down
one pitch the horizontal branch, due to track rounding they *may*
end up on the same track, generating a short.
* Bug: In Anabatic::layerAssign(), during the step of desaturation of
GCells that contains too much terminals (i.e. lot of *local*
congestion), the desaturation threshold was har-coded to 8.
Wich is fine for symbolic cmos but way too low for Flexlib.
End result was that most straight wires where moved towards
the upper layers, creating congestion (imbalance of layer
densities).
Now the parameter:
* "anabatic.saturateRp" (default value:8) is correctly taken
into account.
Jean-Paul Chaput
gatecat