Commit Graph

2629 Commits

Author SHA1 Message Date
Jean-Paul Chaput ab13a02eed Do not make dogleg on segments in non-preferred routing direction.
* Bug: In AutoContactTurn::updateTopology(), in some case we were making
    doglegs on segments in non-preferred routing direction (mostly M2).
    This must be never be done. As, by construction, at least one segment
    of the turn must be in the preferred routing direction, always use
    this one to make the dogleg.
      This bug is likely to explain the remaining "bad spin" in the
    final self-check of the routing data-structure.
2022-05-12 17:54:05 +02:00
Jean-Paul Chaput d3b7251eac NetRoutingExtension::get() failsafe when net is NULL. 2022-05-12 17:53:21 +02:00
Jean-Paul Chaput 5ff81b59ec Separate count from the list of indexes in configuration.IoPin. 2022-05-12 17:52:55 +02:00
Jean-Paul Chaput 59c0ab067b Mangle the "'" in Verilog to VHDL translator. 2022-05-12 17:52:22 +02:00
Jean-Paul Chaput 0a64f3b83d Create and connect dummy signals for unconnected *outputs* in BLIF parser. 2022-05-12 17:51:56 +02:00
Jean-Paul Chaput 921c519bd3 More detailed error message in case of VHDL PORT MAP discrepency. 2022-05-12 17:51:30 +02:00
Jean-Paul Chaput cd60032d9c Added direct management of macro blocks I/O pins in METAL2 & METAL3.
The decoupling of the cell gauge and the routing gauge implies that
the METAL2 & METAL3 terminals of macro blocks cannot be aligned on
the routing tracks anymore. That is, an horizontal METAL2 terminal
will not be on a track axis, but offgrid, so we no longer can use
a METAL2 horizontal segment to connect to it. Making an adjustement
between the offgrid terminal and the on-grid segment has proven
too complex and generating difficult configuration for the router.
Moreover, METLA2 terminal could be fully inside a METAL2 blockage.
So now, when the gauges are decoupled, we connect the METAL2 and
METAL3 the same way we do for METAL1: *from above* in the perpandicular
direction and using a *sliding* VIA. We assume that those kind of
terminals in upper metals are quite long.

* New: In Hurricane::Rectilinear, export the isNonRectangle() method
    to the Python interface.
* New: In CRL::RoutingGauge, add function isSuperPitched() with the
    associated boolean attribute. Set to true when each pitch of
    each layer is independant (not low fractional multiples).
* New: In AnabaticEngine, add the ability to temporarily disable the
    canonize() operation (mainly used in dogleg creation).
* New: In AutoSegment::canonize(), do nothing if the operation is
    disabled by AnabaticEngine.
* Bug: In Session::_revalidateTopology(), disable the canonization
    during the topology updating of a net. Too early canonization
    was occuring in makeDogleg() leading to incoherencies when
    performing the later canonization stage over the complete net.
    Mostly occured in the initial build stage of the net.
* New: In GCell, add function postGlobalAnnotate(), if a layer
    is fully blocked (above 0.9), typically, under a blockage,
    add a further capacity decrease of 2 on the edges. So we may
    handle a modicum of doglegs.
* Bug; In GCell::addBlockage(), removeContact(), removeHSegment()
    and removeVSegment(), forgot to set the Invalidated flag.
    This may have lead to innacurate densities.
* Change: In GCell::updateDensity(), more complex setting of the
    GoStraight flag. This flag is now set if we don't have two
    *contiguous* below 60% of density. We need free contiguous
    layers to make doglegs.
* New: In NetBuilder, now manage a current state flag along
    with the state flag of the *source* GCell. This flag is used
    to tell if the GCell needs it's *global* routing to be done
    using the upper layers (METAL4 & METAL5) instead of the
    lower ones.
* New: In NetBuilder::setStartHook(), set the state flag of the
    GCell to ToUpperRouting when processing a global routing
    articulation and one of the base layer is obstructed
    above 0.9.
      In GCell with terminals, also set ToUpperRouting when there
    are some in METAL2 / METAL3 and the gauge is not super-pitched.
* New: In NetBuilder, function isInsideBlockage(), to check if a
    terminal is completely or partially enclosed in a blockage.
* Change: In NetBuilderHV::doRp_AutoContact(), remove support for
    trying to put on grid misaligned METAL2/METAL3.
      Instead systematically access them from above.
      Do not cover with fixed protection terminals that are already
    enclosed in blockages.
* Bug: In NetBuilderHV::doRp_AutoContact(), always add the terminal
    contact in the requested GCell and not the target/source one,
    in case the terminal span several GCells.
* Change: In NetBuilderHV::doRp_Access(), create the local wiring
    according to the RoutingPad layer.
* Change: In NetBuilderHV::_do_xG(), _do_2G(),
    create the global wiring in upper layers, according to the
    ToUpperRouting flag.
* Change: In NetBuilderHV::_do_xG_xM3(), now delegate to
    _do_xG_xM3_baseRouting() and _do_xG_xM3_upperRouting() if the
    density at terminal level is above 0.5.
* New: NetBuilderHV::_do_xG_xM3_baseRouting() and
    _do_xG_xM3_upperRouting() separated function to manage the
    local routing.
* Change: In NetBuilder::_do_globalSegment(), if the currently
    processed GCell or it's source is in ToUpperRouting mode,
    move up the global segment. Do *not* use the moveUp() function
    which would create doglegs unwanted at this stage.
* New: In KatanaEngine::annotateGlobalGraph(), call postGlobalAnnotate()
    on the GCell after the blockages have been taken into accound to
    add the penalty.
* Bug: In Track::getPrevious(), correctly manage the 0 value for the
    index argument. Strange it didn't show earlier.
      Same goes for Track::expandFreeInterval().
2022-04-27 21:56:41 +02:00
Jean-Paul Chaput 908231c4c4 Missing BigVia import and some typos. 2022-04-03 13:19:49 +02:00
Jean-Paul Chaput 4ffd91822f Added support for SPICE terminal ordering from .spi files.
After a Cell has been created in memory (by parsers or Python scripts)
we can annotate it with the Spice parser so it will know the right
order with which to create the subcircuit call ('x').

* New: In CRL::Spice::load(), add support to read the ".subckt" card
    and guess the right ordering for generating the 'x' (subcircuit
    card call).
* Bug: In Spice::SpiceBit & Spice::BitExtension, when a Net bit property
    is removed, if it's the currently cached property in BitExtension
    it may lead to a crash. So when a property is destroyed, we must
    also clear the cache (see remove(), clearCache() & onReleasedby()).
      I'm wary that this could also happen on other kind of cached
    extensions...
* New: In CRL::NamingScheme, new method vhdlToVlog() to translate back
    VHDL net name into Verilog. Currently only changes "()" into "[]".
    Used to generate the commented SPICE interface for Alliance compliance.
* Change: In Spice::Entity, previously all the ordering where removed
    between each run of the SPICE parser, but the orders read from
    SPICE file (mostly standard cells) must be kept. So add a flag
    ReferenceCell to prevent the removal by ::destroyAll().
2022-04-03 13:18:42 +02:00
Jean-Paul Chaput fd624f03b6 Forgot emiting "layoutAbouttobechanged" in NetlistModel::setCell().
* Bug: In NetlistModel::setCell() template, forgot to send the
    "layoutAboutToBeChanged" signal before disconnecting the
    netlist datas. This seemed to go unnoticed until ported
    under Qt5. Was generating strange random core dump when
    running the engines with a net kept selected. Disgraceful
    crash during demos...
2022-01-26 19:41:39 +01:00
Jean-Paul Chaput 7f936367f8 Fix deletion bug in Selector::_preDestroy().
* Bug: In Selector::_preDestroy(), *do not* iterate over the _cellWidgets
    map as we destroy it's elements! We end up in destroyed ones...
    Instead destroy the first one until the map is empty.
2022-01-26 19:34:31 +01:00
Jean-Paul Chaput a5d92ecc29 Beautification, display "boundaries" below everything else.
* Change: In CellWidget::_redraw(), the boundaries, that is, instances
    abutment boxes where drawn *after* everything else, so they where
    hiding more interesting informations (especially at low zoom level)
    like routing wires.
      Now draw them *first* so they are *below*.
2022-01-26 19:31:01 +01:00
Jean-Paul Chaput 6210d312fe Correct the image snaphot generation (CellImage).
* Change: In CellImage::setScreenCellWidget, fully copy the display
    settings from the reference widget (not just part of them).
* Bug: In CellImage::toImage(), if the abutment box of the displayed
    cell is not *fully* includer in the viewer area, do *not* try to
    reframe it. The reframe() method seems to be buggy, works OK
    just without calling it.
2022-01-26 19:25:50 +01:00
Jean-Paul Chaput 08b951047c Update to support BFD 2.35.2 to generate file/line in stack traces. 2022-01-26 19:19:01 +01:00
Jean-Paul Chaput b54380e05d Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel 2022-01-15 17:28:44 +01:00
Jean-Paul Chaput b6192e78c1 Minor documentation patchs to work with RHEL9. 2022-01-15 17:28:21 +01:00
Jean-Paul Chaput 1d839711ad Merge branch 'lefdef-out' into 'devel'
Bind DEF/LEF export to Python and make it useful for real processes

See merge request vlsi-eda/coriolis!14
2022-01-14 13:42:39 +00:00
Jean-Paul Chaput c805f4d6e4 Fix stupid mistake of "trace" import in core2chip.cmos.py. 2022-01-13 11:16:07 +01:00
Jean-Paul Chaput 22dd3ddc73 Remove bison generated yy.tab.h. Included by mistake. 2022-01-12 16:31:46 +01:00
Jean-Paul Chaput c41bd36279 Small code presentation improvements. 2022-01-12 16:27:47 +01:00
Jean-Paul Chaput 762e25adde More Python 3 corrections.
* Change: In unicorn/python/unicornInit.py, when iterating over all the
    loaded modules, now we have "namespace" that have a __file__
    attribute which is set to None. Skip them.
* Change: In stratus1/st_net.py, "is" must be replaced by "==" when
    doing string comparison.
* Change: In stratus1/st_parser.py, open file in "rb" mode instead
    of "r" (so we get a bytestream as now required by Python).
2022-01-12 16:25:01 +01:00
gatecat 6c66208e0c def: Write route segments
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-12 14:14:15 +00:00
gatecat 9635cc3311 lef: Fix MANUFACTURINGGRID order
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-12 13:42:03 +00:00
gatecat c4ef465c41 def: Fix order of instance transforms
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 19:45:24 +00:00
gatecat 4250c5bec7 def: Fix export of pins
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 18:47:13 +00:00
gatecat a8dd84838b def: Fix export units for non-lambda processes
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
gatecat ddb684bfe1 defexport: Make it useful for real processes
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
gatecat 4884a5d6dc crlcore: Add Python bindings for DEF export
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
gatecat 2f1caca812 lefexport: Make it useful for real processes
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
gatecat e1c5366fef crlcore: Add Python bindings for LEF export
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
Jean-Paul Chaput 0d7deafe81 Remove mistakenly commited backup file. 2022-01-01 17:15:41 +01:00
Jean-Paul Chaput 581f557aef Fix: The SelectionPopup widget was deleted after first use.
* Bug: In Viewer::SelectionPopup(), the window attribute
   Qt::WA_DeleteOnClose was *not* cleared. So the window was deleted
   after first use while it was though staying allocated.
     Again, generating weird crashes.
     Took the occasion to slightly redesign the behavior to select
   and highlight individual components.
2022-01-01 16:47:09 +01:00
Jean-Paul Chaput 0c54d109cc Fix: Do not return transient string in PyTypeManager.
* Bug: In Isobar3::PyTypeManager, the accessors _getCppTypeName() and
    _getPyTypeName() where returning string *by value*, hence, short
    lived copies.
      But, in _setupPyType() and _addToModule(), as we interface with
    the Python/C API, we extract the c_str(). Which where removed as
    we used temporary objects. Leading to memory corruption and weird
    crashes.
      Now returns "const string&" so the c_str() stays allocated.
2022-01-01 16:46:41 +01:00
Jean-Paul Chaput 9aaaf33e6e Manage more interrupt signals in CRL::System::_trapSig(). Display value. 2022-01-01 16:46:15 +01:00
Jean-Paul Chaput 550b087f05 Takes even further appart the HTree buffer input/output. 2021-12-31 16:48:45 +01:00
Jean-Paul Chaput 084eee3b39 Added support for RHEL9. 2021-12-31 16:35:38 +01:00
Jean-Paul Chaput 5f8a0a944c Display bug for non-rectangular components in DrawinQuery::drawGo().
* Bug: In CellWidget::DrawingQuery::drawGo(), the display condition was
    wrong, it was requiring *both* width & height to be above the display
    threshold. Either one is sufficient to activate the display.
      Was causing the selective diseapearance of gates at low zoom level
    and printed version.
* Change: In CellPrinter, force the display threshold to one pixel in it's
    internal CellWidget used for printing.
2021-12-25 15:23:49 +01:00
Jean-Paul Chaput fdce75fdad Fix bad computation of perpandicular free space in DataNegociate, again.
* Bug: In Katana::DataNegociate::update(), when computing the length of
    source & target extension on a perpandicular segment, must use the
    extensions of the *directly* connected AutoSegment (the baseSegment)
    and not the canonical one that may be different, so with unrelated
    extensions.
2021-12-25 15:23:23 +01:00
Jean-Paul Chaput 104c043416 In the H-Tree, shift vertical H wire one pitch to the left.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), the RoutingPads
    for the input and output of the buffer where sometimes put too
    close from each others, giving the pitch of the vertical tracks.
    Now shift one pitch left the vertical branchs of the H-Tree.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), also shift down
    one pitch the horizontal branch, due to track rounding they *may*
    end up on the same track, generating a short.
2021-12-25 15:22:58 +01:00
Jean-Paul Chaput 64056d25ee Layer assignment step was ignoring the number of RoutingPad threshold.
* Bug: In Anabatic::layerAssign(), during the step of desaturation of
    GCells that contains too much terminals (i.e. lot of *local*
    congestion), the desaturation threshold was har-coded to 8.
    Wich is fine for symbolic cmos but way too low for Flexlib.
      End result was that most straight wires where moved towards
    the upper layers, creating congestion (imbalance of layer
    densities).
      Now the parameter:
        * "anabatic.saturateRp" (default value:8) is correctly taken
	  into account.
2021-12-22 15:52:22 +01:00
Jean-Paul Chaput a4ad671739 Fix too naive obstacle detection on non-prefered metal2 wires.
* Fix: In Manipulator::avoidBlockage(), the dedicated function to check if
    there is an obstacle in the way of a non-prefered routing wire (done
    for metal2 connecting to terminals only) was too naive.
      We were checking the tracks for obstacles crossing exactly the axis
    of the segment. And for near-miss this is not enough. Now check on
    the whole x-span to be used by the segment.
      Code borrowed and simplified from Track::addOverlapcost().
* Change: In Manipulator::moveUp(), the default value for the extra
    reservation allowing a long wire to move up need to be customized
    for Flexlib/StdCellLib (allow successful routing of ChipFlow/MPW4).
      Add two new configuration parameters to katana:
        * "katana.longWireUpThresold1" : the length, expressed in number
	  of *slice height* above which a global wire is considered a
	  *long* wire (not close interconnect).
        * "katana.longWireUpReserve1" : the extra number of free tracks
	  that must remains free in the up layer after the move up,
	  in each GCell traversed by the wire. Expressed in number of
	  tracks, but can be non-integer (float, for instance: 1.5).
2021-12-21 16:13:31 +01:00
Jean-Paul Chaput 92e5f3fa4d Update ad-hoc patch for obstacles for Flexlib & StdCellLib.
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), to avaid tracks too
    close to an offgrid obstacle in the preferred routing direction, we
    expand the width/height of the segment by one pitch. BUT it seems to
    still be too close for Flexlib and StdCellLib, so there is an ad-hoc
    patch based on the *name* of the cell library. Update it to take
    "StdCellLib" into account.
2021-12-21 16:13:07 +01:00
Jean-Paul Chaput 3fa8d516bc Fix bad computation of perpandicular free space in DataNegociate.
NOTE: This is likely to explain why we still got overlap in the
      track coherency check in very rare occasions.

* Bug: In Katana::DataNegociate::update(), when computing the allowed
    free interval for the segment axis deduced from the perpandicularly
    connex segments, we account for the extension of the connecting
    VIA. Those extension varies according to the kind of VIA and are
    given by getExtensionCap().
      We were accounting for the source & target extension VIA on the
    parallel segments, assuming that source/target would not swap when
    the perpandicular is moved. Which is *not* true.
      Now account for the extension of the *connecting* VIA on all ends.
* Change: In AutoSegment::getTopologicalInfos(), enrich the list of
    perpandicularly connected segment with wether they are connex by
    their *source* or *target* contact. Mainly to be used by
    DataNegociate::update().
2021-12-18 17:45:17 +01:00
Jean-Paul Chaput ae1f08f039 Change SkyWater130 Caravel harness connecting strategy.
* Change: In cumulus/plugins/core2chip, instead of the user providing
    an explicit mapping towards the harness I/O pins, we expect that
    the core block must have I/O pins with names matching thoses of
    the harness. That way, connections are automatically made.
* Change: In cumulus/plugins/block/htree, if the root signal of the
    H-Tree is a bit from a vector (like "io_in(0)"), then remove the
    vector index notation on all the stem name of all the sub-nets.
    Done by the unbitify() function: "io_in(0)" => "io_in_bit0".
2021-12-17 15:58:57 +01:00
Jean-Paul Chaput 76d468f6d5 Change in feed & tie managements to fill the empty row spaces.
* Change: In EtesianEngine::_postCreate(), issue a warning if the list of
    feeds is empy (configuration: "cfg.etesian.feedNames").
* New: Add a FeedCeels::getFeedByWidth() method to get feeds by their
    width in DbU::Unit and not only pitches.
* Change: In Placement::Slice::fillHole(), invert the tie filling and
    feeds filling stage. Now we first try to fill the row hole with
    feeds, using the widest first, and if they are not configured or
    too wide, use the tie.
      As the tie *should* also be integrated in the feed list, we may
    suppress altogether the fallback tie filling step. Keep it for now.
* Change: In Placement::slice::createDiodeUnder(), the inserted diode
    *may* be smaller than the feed it replace. So, in this case, add
    a complementary feed to fill the gap.
    NOTE 1: Out of lazyness, we add only *one* complementary filler
            cell. So there *must* be one of a width wich correspond
	    exactly to the difference between the original feed and
	    the diode. Otherwise, gap will remains.
    NOTE 2: With wider feed cells, they may cross the GCell border.
            But we must insert the diode under the GCell, otherwise
	    the global routing will be defective. So, for now, reject
	    feeds that cross the boundary. Must be done more smartly
	    by inserting the diode over the left or right side of
	    the feed.
2021-12-17 15:58:13 +01:00
Jean-Paul Chaput 4ab6888b94 Fix Pin managment on north & east side of the cell abutment box.
* Change: In AnabaticEngine::setupPrerouteds(), take into account the
    number of Pins. Now consider a net containing multiple Pins and, at most,
    one segment as *non-routed".
      This case may specifically happens for nets with pins on the north
    and east side, which are slightly *inside* the abutment box (to be
    seen by the router) and draw with them their *outside* direct
    connection wire.
* Bug: In cumulus/plugins.chip.CoreWire, no longer put the north or
    east side external Pin *exacyly* on the abutment box but *one pitch*
    inside so they are correctly seens by the P&R (must be *inside*
    the area of a GCell).
2021-12-17 15:56:15 +01:00
Jean-Paul Chaput 67ca0997c3 Merge branch 'fix-blif-zero-one' into 'devel'
blif: Improve detection of zero/one net by requiring it to be external

See merge request vlsi-eda/coriolis!12
2021-12-11 21:07:18 +00:00
Jean-Paul Chaput 73296503ad Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel 2021-12-11 22:00:10 +01:00
Jean-Paul Chaput fe32916d14 Add support for the SkyWater130 Caravel harness to "core2chip".
It is now possible to automatically nest a core block inside a harness
frame, like we do for an ordinary chip whith I/O pads. The DEF harness
file "user_project_wrapper.def" must be made available though the block
configuration variable:
   conf.cfg.harness.path = './user_project_wrapper.def'
A first small example is given in:
   alliance-check-toolkit/benchs/counter/sky130_c4m
The harness layout is stripped from it's native power grid (but keep
the power ring). I/O pad information in block/configuration is
slightly "bent* to manage pins instead of complete I/O pads.

* Bug: In cumulus/plugins.block.Block.setupAb(), the routingBb was not
    set up when working in chip mode. Now set (to the corona AB).
* Change: In cumulus/plugins.chip.__init__, move there the CoreWire
    class (from chip/pads.py) so it can be shared with the harness
    version of pads.py.
* Change: In cumulus/plugins.chip.powerplane, compute the intersection
    between the vertical supply stripes and the deep horizontal power
    lines in a smarter fashion, so two (or more) vertically contiguous
    BigVias are merged into one (two BigVia side by side where causing
    mimimal spacing distance violation on the cut in Sky130).
2021-12-11 19:52:31 +01:00
Jean-Paul Chaput 2ca9e162ef Allow the detailed routing to be build from non-bottom P&R layers.
* New: In Anabatic::AutoSegment::create(), allow the created segment to
    be in any supported routing layer, and not only the bottom H & V.
    Modifications impact the *two* overload of the function.
* Change: In Anabatic::NetBuilderHV::doRp_AutoContacts(), for punctual
    METAL1, the protection has to be in METAL2. Bump the layer depth
    to correctly use the updated verstion of AutoSegment::create().
* Change: In AnabaticEngine::checkPlacement(), for the Pin, check that
    it's layer is in the routing gauge before anything else.
* New: In Katana::NegociateWindow::createTrackSegment(), if the track
    nearest the segment axis (refTrack) do not exists, call a
    breakpoint just before crashing.
2021-12-11 19:51:24 +01:00