caravel/signoff/caravel_core/metrics.csv

1	Metric	Value
2	design__instance__count	47420
3	design__instance__area	12590500
4	design__instance_unmapped__count	0
5	synthesis__check_error__count	0
6	design__die__bbox	0.0 0.0 3165.0 4767.0
7	design__core__bbox	10.12 10.88 3154.68 4754.56
8	design__io	633
9	design__die__area	15087600
10	design__core__area	14916800
11	design__instance__count__stdcell	47326
12	design__instance__area__stdcell	141326
13	design__instance__count__macros	94
14	design__instance__area__macros	12449200
15	design__instance__utilization	0.844051
16	design__instance__utilization__stdcell	0.0572728
17	design__power_grid_violation__count__net:vccd1	10
18	design__power_grid_violation__count__net:vssd1	12
19	design__power_grid_violation__count__net:vssio	143
20	design__power_grid_violation__count__net:vccd	53152
21	design__power_grid_violation__count__net:vdda1	804
22	design__power_grid_violation__count__net:vssa2	860
23	design__power_grid_violation__count__net:vssd2	800
24	design__power_grid_violation__count__net:vdda2	804
25	design__power_grid_violation__count__net:vddio	143
26	design__power_grid_violation__count__net:vssd	1249
27	design__power_grid_violation__count__net:vccd2	804
28	design__power_grid_violation__count__net:vssa1	828
29	design__power_grid_violation__count	59609
30	timing__drv__floating__nets	34
31	timing__drv__floating__pins	0
32	design__instance__displacement__total	0
33	design__instance__displacement__mean	0
34	design__instance__displacement__max	0
35	route__wirelength__estimated	1617690
36	design__violations	0
37	design__instance__count__setup_buffer	0
38	design__instance__count__hold_buffer	0
39	antenna__violating__nets	98
40	antenna__violating__pins	98
41	route__antenna_violation__count	98
42	route__net	7904
43	route__net__special	12
44	route__drc_errors__iter:1	9400
45	route__wirelength__iter:1	1674839
46	route__drc_errors__iter:2	4061
47	route__wirelength__iter:2	1673179
48	route__drc_errors__iter:3	3333
49	route__wirelength__iter:3	1672916
50	route__drc_errors__iter:4	1150
51	route__wirelength__iter:4	1675079
52	route__drc_errors__iter:5	670
53	route__wirelength__iter:5	1675159
54	route__drc_errors__iter:6	375
55	route__wirelength__iter:6	1675000
56	route__drc_errors__iter:7	210
57	route__wirelength__iter:7	1674925
58	route__drc_errors__iter:8	199
59	route__wirelength__iter:8	1674923
60	route__drc_errors__iter:9	199
61	route__wirelength__iter:9	1674923
62	route__drc_errors__iter:10	198
63	route__wirelength__iter:10	1674922
64	route__drc_errors__iter:11	22
65	route__wirelength__iter:11	1674959
66	route__drc_errors__iter:12	1
67	route__wirelength__iter:12	1674999
68	route__drc_errors__iter:13	0
69	route__wirelength__iter:13	1674999
70	route__drc_errors	0
71	route__wirelength	1674999
72	route__vias	63530
73	route__vias__singlecut	63530
74	route__vias__multicut	0
75	design__disconnected_pin__count	4
76	design__critical_disconnected_pin__count	0
77	route__wirelength__max	4068.8
78	design__max_slew_violation__count__corner:nom_tt_025C_1v80	62
79	design__max_fanout_violation__count__corner:nom_tt_025C_1v80	2749
80	design__max_cap_violation__count__corner:nom_tt_025C_1v80	20
81	power__internal__total	0.00517409248277545
82	power__switching__total	0.009297482669353485
83	power__leakage__total	0.0000018622023389980313
84	power__total	0.014473438262939453
85	clock__skew__worst_hold__corner:nom_tt_025C_1v80	7.539481
86	clock__skew__worst_setup__corner:nom_tt_025C_1v80	8.092601
87	timing__hold__ws__corner:nom_tt_025C_1v80	0.223158
88	timing__setup__ws__corner:nom_tt_025C_1v80	4.14658
89	timing__hold__tns__corner:nom_tt_025C_1v80	0.0
90	timing__setup__tns__corner:nom_tt_025C_1v80	0.0
91	timing__hold__wns__corner:nom_tt_025C_1v80	0.0
92	timing__setup__wns__corner:nom_tt_025C_1v80	0.0
93	timing__hold_vio__count__corner:nom_tt_025C_1v80	0
94	timing__hold_r2r__ws__corner:nom_tt_025C_1v80	0.223158
95	timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80	0
96	timing__setup_vio__count__corner:nom_tt_025C_1v80	0
97	timing__setup_r2r__ws__corner:nom_tt_025C_1v80	6.124457
98	timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80	0
99	timing__unannotated_net__count__corner:nom_tt_025C_1v80	1413
100	timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80	0
101	design__max_slew_violation__count__corner:nom_ss_100C_1v60	884
102	design__max_fanout_violation__count__corner:nom_ss_100C_1v60	2749
103	design__max_cap_violation__count__corner:nom_ss_100C_1v60	633
104	clock__skew__worst_hold__corner:nom_ss_100C_1v60	10.114737
105	clock__skew__worst_setup__corner:nom_ss_100C_1v60	11.186316
106	timing__hold__ws__corner:nom_ss_100C_1v60	0.365902
107	timing__setup__ws__corner:nom_ss_100C_1v60	0.47358
108	timing__hold__tns__corner:nom_ss_100C_1v60	0.0
109	timing__setup__tns__corner:nom_ss_100C_1v60	0.0
110	timing__hold__wns__corner:nom_ss_100C_1v60	0.0
111	timing__setup__wns__corner:nom_ss_100C_1v60	0.0
112	timing__hold_vio__count__corner:nom_ss_100C_1v60	0
113	timing__hold_r2r__ws__corner:nom_ss_100C_1v60	0.67361
114	timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60	0
115	timing__setup_vio__count__corner:nom_ss_100C_1v60	0
116	timing__setup_r2r__ws__corner:nom_ss_100C_1v60	0.47358
117	timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60	0
118	timing__unannotated_net__count__corner:nom_ss_100C_1v60	1413
119	timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60	0
120	design__max_slew_violation__count__corner:nom_ff_n40C_1v95	60
121	design__max_fanout_violation__count__corner:nom_ff_n40C_1v95	2749
122	design__max_cap_violation__count__corner:nom_ff_n40C_1v95	20
123	clock__skew__worst_hold__corner:nom_ff_n40C_1v95	6.394931
124	clock__skew__worst_setup__corner:nom_ff_n40C_1v95	6.699955
125	timing__hold__ws__corner:nom_ff_n40C_1v95	0.079782
126	timing__setup__ws__corner:nom_ff_n40C_1v95	5.485413
127	timing__hold__tns__corner:nom_ff_n40C_1v95	0.0
128	timing__setup__tns__corner:nom_ff_n40C_1v95	0.0
129	timing__hold__wns__corner:nom_ff_n40C_1v95	0.0
130	timing__setup__wns__corner:nom_ff_n40C_1v95	0.0
131	timing__hold_vio__count__corner:nom_ff_n40C_1v95	0
132	timing__hold_r2r__ws__corner:nom_ff_n40C_1v95	0.079782
133	timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95	0
134	timing__setup_vio__count__corner:nom_ff_n40C_1v95	0
135	timing__setup_r2r__ws__corner:nom_ff_n40C_1v95	8.43183
136	timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95	0
137	timing__unannotated_net__count__corner:nom_ff_n40C_1v95	1413
138	timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95	0
139	design__max_slew_violation__count__corner:min_tt_025C_1v80	4
140	design__max_fanout_violation__count__corner:min_tt_025C_1v80	2749
141	design__max_cap_violation__count__corner:min_tt_025C_1v80	1
142	clock__skew__worst_hold__corner:min_tt_025C_1v80	7.361092
143	clock__skew__worst_setup__corner:min_tt_025C_1v80	7.886006
144	timing__hold__ws__corner:min_tt_025C_1v80	0.259431
145	timing__setup__ws__corner:min_tt_025C_1v80	4.370804
146	timing__hold__tns__corner:min_tt_025C_1v80	0.0
147	timing__setup__tns__corner:min_tt_025C_1v80	0.0
148	timing__hold__wns__corner:min_tt_025C_1v80	0.0
149	timing__setup__wns__corner:min_tt_025C_1v80	0.0
150	timing__hold_vio__count__corner:min_tt_025C_1v80	0
151	timing__hold_r2r__ws__corner:min_tt_025C_1v80	0.259431
152	timing__hold_r2r_vio__count__corner:min_tt_025C_1v80	0
153	timing__setup_vio__count__corner:min_tt_025C_1v80	0
154	timing__setup_r2r__ws__corner:min_tt_025C_1v80	6.463247
155	timing__setup_r2r_vio__count__corner:min_tt_025C_1v80	0
156	timing__unannotated_net__count__corner:min_tt_025C_1v80	1413
157	timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80	0
158	design__max_slew_violation__count__corner:min_ss_100C_1v60	27
159	design__max_fanout_violation__count__corner:min_ss_100C_1v60	2749
160	design__max_cap_violation__count__corner:min_ss_100C_1v60	135
161	clock__skew__worst_hold__corner:min_ss_100C_1v60	9.838772
162	clock__skew__worst_setup__corner:min_ss_100C_1v60	10.867458
163	timing__hold__ws__corner:min_ss_100C_1v60	0.531116
164	timing__setup__ws__corner:min_ss_100C_1v60	1.108624
165	timing__hold__tns__corner:min_ss_100C_1v60	0.0
166	timing__setup__tns__corner:min_ss_100C_1v60	0.0
167	timing__hold__wns__corner:min_ss_100C_1v60	0.0
168	timing__setup__wns__corner:min_ss_100C_1v60	0.0
169	timing__hold_vio__count__corner:min_ss_100C_1v60	0
170	timing__hold_r2r__ws__corner:min_ss_100C_1v60	0.669473
171	timing__hold_r2r_vio__count__corner:min_ss_100C_1v60	0
172	timing__setup_vio__count__corner:min_ss_100C_1v60	0
173	timing__setup_r2r__ws__corner:min_ss_100C_1v60	1.108624
174	timing__setup_r2r_vio__count__corner:min_ss_100C_1v60	0
175	timing__unannotated_net__count__corner:min_ss_100C_1v60	1413
176	timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60	0
177	design__max_slew_violation__count__corner:min_ff_n40C_1v95	4
178	design__max_fanout_violation__count__corner:min_ff_n40C_1v95	2749
179	design__max_cap_violation__count__corner:min_ff_n40C_1v95	1
180	clock__skew__worst_hold__corner:min_ff_n40C_1v95	6.269701
181	clock__skew__worst_setup__corner:min_ff_n40C_1v95	6.555291
182	timing__hold__ws__corner:min_ff_n40C_1v95	0.104456
183	timing__setup__ws__corner:min_ff_n40C_1v95	5.689445
184	timing__hold__tns__corner:min_ff_n40C_1v95	0.0
185	timing__setup__tns__corner:min_ff_n40C_1v95	0.0
186	timing__hold__wns__corner:min_ff_n40C_1v95	0.0
187	timing__setup__wns__corner:min_ff_n40C_1v95	0.0
188	timing__hold_vio__count__corner:min_ff_n40C_1v95	0
189	timing__hold_r2r__ws__corner:min_ff_n40C_1v95	0.104456
190	timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95	0
191	timing__setup_vio__count__corner:min_ff_n40C_1v95	0
192	timing__setup_r2r__ws__corner:min_ff_n40C_1v95	8.631856
193	timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95	0
194	timing__unannotated_net__count__corner:min_ff_n40C_1v95	1413
195	timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95	0
196	design__max_slew_violation__count__corner:max_tt_025C_1v80	91
197	design__max_fanout_violation__count__corner:max_tt_025C_1v80	2749
198	design__max_cap_violation__count__corner:max_tt_025C_1v80	25
199	clock__skew__worst_hold__corner:max_tt_025C_1v80	7.697963
200	clock__skew__worst_setup__corner:max_tt_025C_1v80	8.276884
201	timing__hold__ws__corner:max_tt_025C_1v80	0.193509
202	timing__setup__ws__corner:max_tt_025C_1v80	3.880933
203	timing__hold__tns__corner:max_tt_025C_1v80	0.0
204	timing__setup__tns__corner:max_tt_025C_1v80	0.0
205	timing__hold__wns__corner:max_tt_025C_1v80	0.0
206	timing__setup__wns__corner:max_tt_025C_1v80	0.0
207	timing__hold_vio__count__corner:max_tt_025C_1v80	0
208	timing__hold_r2r__ws__corner:max_tt_025C_1v80	0.193509
209	timing__hold_r2r_vio__count__corner:max_tt_025C_1v80	0
210	timing__setup_vio__count__corner:max_tt_025C_1v80	0
211	timing__setup_r2r__ws__corner:max_tt_025C_1v80	5.939717
212	timing__setup_r2r_vio__count__corner:max_tt_025C_1v80	0
213	timing__unannotated_net__count__corner:max_tt_025C_1v80	1413
214	timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80	0
215	design__max_slew_violation__count__corner:max_ss_100C_1v60	2026
216	design__max_fanout_violation__count__corner:max_ss_100C_1v60	2749
217	design__max_cap_violation__count__corner:max_ss_100C_1v60	1521
218	clock__skew__worst_hold__corner:max_ss_100C_1v60	10.359847
219	clock__skew__worst_setup__corner:max_ss_100C_1v60	11.472188
220	timing__hold__ws__corner:max_ss_100C_1v60	0.210718
221	timing__setup__ws__corner:max_ss_100C_1v60	0.079025
222	timing__hold__tns__corner:max_ss_100C_1v60	0.0
223	timing__setup__tns__corner:max_ss_100C_1v60	0.0
224	timing__hold__wns__corner:max_ss_100C_1v60	0.0
225	timing__setup__wns__corner:max_ss_100C_1v60	0.0
226	timing__hold_vio__count__corner:max_ss_100C_1v60	0
227	timing__hold_r2r__ws__corner:max_ss_100C_1v60	0.67373
228	timing__hold_r2r_vio__count__corner:max_ss_100C_1v60	0
229	timing__setup_vio__count__corner:max_ss_100C_1v60	0
230	timing__setup_r2r__ws__corner:max_ss_100C_1v60	0.079025
231	timing__setup_r2r_vio__count__corner:max_ss_100C_1v60	0
232	timing__unannotated_net__count__corner:max_ss_100C_1v60	1413
233	timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60	0
234	design__max_slew_violation__count__corner:max_ff_n40C_1v95	89
235	design__max_fanout_violation__count__corner:max_ff_n40C_1v95	2749
236	design__max_cap_violation__count__corner:max_ff_n40C_1v95	25
237	clock__skew__worst_hold__corner:max_ff_n40C_1v95	6.509506
238	clock__skew__worst_setup__corner:max_ff_n40C_1v95	6.83562
239	timing__hold__ws__corner:max_ff_n40C_1v95	0.06435
240	timing__setup__ws__corner:max_ff_n40C_1v95	5.224452
241	timing__hold__tns__corner:max_ff_n40C_1v95	0.0
242	timing__setup__tns__corner:max_ff_n40C_1v95	0.0
243	timing__hold__wns__corner:max_ff_n40C_1v95	0.0
244	timing__setup__wns__corner:max_ff_n40C_1v95	0.0
245	timing__hold_vio__count__corner:max_ff_n40C_1v95	0
246	timing__hold_r2r__ws__corner:max_ff_n40C_1v95	0.06435
247	timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95	0
248	timing__setup_vio__count__corner:max_ff_n40C_1v95	0
249	timing__setup_r2r__ws__corner:max_ff_n40C_1v95	8.318182
250	timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95	0
251	timing__unannotated_net__count__corner:max_ff_n40C_1v95	1413
252	timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95	0
253	design__max_slew_violation__count	2026
254	design__max_fanout_violation__count	2749
255	design__max_cap_violation__count	1521
256	clock__skew__worst_hold	10.359847
257	clock__skew__worst_setup	6.555291
258	timing__hold__ws	0.06435
259	timing__setup__ws	0.079025
260	timing__hold__tns	0.0
261	timing__setup__tns	0.0
262	timing__hold__wns	0.0
263	timing__setup__wns	0.0
264	timing__hold_vio__count	0
265	timing__hold_r2r__ws	0.06435
266	timing__hold_r2r_vio__count	0
267	timing__setup_vio__count	0
268	timing__setup_r2r__ws	0.079025
269	timing__setup_r2r_vio__count	0
270	timing__unannotated_net__count	1413
271	timing__unannotated_net_filtered__count	0
272	design__xor_difference__count	0
273	magic__drc_error__count	55
274	klayout__drc_error__count	0
275	magic__illegal_overlap__count	0
276	design__lvs_device_difference__count	3
277	design__lvs_net_difference__count	2
278	design__lvs_property_fail__count	0
279	design__lvs_error__count	172
280	design__lvs_unmatched_device__count	17
281	design__lvs_unmatched_net__count	71
282	design__lvs_unmatched_pin__count	79