Metric,Value
design__instance__count,47420
design__instance__area,12590500
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__die__bbox,0.0 0.0 3165.0 4767.0
design__core__bbox,10.12 10.88 3154.68 4754.56
design__io,633
design__die__area,15087600
design__core__area,14916800
design__instance__count__stdcell,47326
design__instance__area__stdcell,141326
design__instance__count__macros,94
design__instance__area__macros,12449200
design__instance__utilization,0.844051
design__instance__utilization__stdcell,0.0572728
design__power_grid_violation__count__net:vccd1,10
design__power_grid_violation__count__net:vssd1,12
design__power_grid_violation__count__net:vssio,143
design__power_grid_violation__count__net:vccd,53152
design__power_grid_violation__count__net:vdda1,804
design__power_grid_violation__count__net:vssa2,860
design__power_grid_violation__count__net:vssd2,800
design__power_grid_violation__count__net:vdda2,804
design__power_grid_violation__count__net:vddio,143
design__power_grid_violation__count__net:vssd,1249
design__power_grid_violation__count__net:vccd2,804
design__power_grid_violation__count__net:vssa1,828
design__power_grid_violation__count,59609
timing__drv__floating__nets,34
timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,1617690
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,0
antenna__violating__nets,98
antenna__violating__pins,98
route__antenna_violation__count,98
route__net,7904
route__net__special,12
route__drc_errors__iter:1,9400
route__wirelength__iter:1,1674839
route__drc_errors__iter:2,4061
route__wirelength__iter:2,1673179
route__drc_errors__iter:3,3333
route__wirelength__iter:3,1672916
route__drc_errors__iter:4,1150
route__wirelength__iter:4,1675079
route__drc_errors__iter:5,670
route__wirelength__iter:5,1675159
route__drc_errors__iter:6,375
route__wirelength__iter:6,1675000
route__drc_errors__iter:7,210
route__wirelength__iter:7,1674925
route__drc_errors__iter:8,199
route__wirelength__iter:8,1674923
route__drc_errors__iter:9,199
route__wirelength__iter:9,1674923
route__drc_errors__iter:10,198
route__wirelength__iter:10,1674922
route__drc_errors__iter:11,22
route__wirelength__iter:11,1674959
route__drc_errors__iter:12,1
route__wirelength__iter:12,1674999
route__drc_errors__iter:13,0
route__wirelength__iter:13,1674999
route__drc_errors,0
route__wirelength,1674999
route__vias,63530
route__vias__singlecut,63530
route__vias__multicut,0
design__disconnected_pin__count,4
design__critical_disconnected_pin__count,0
route__wirelength__max,4068.8
design__max_slew_violation__count__corner:nom_tt_025C_1v80,62
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2749
design__max_cap_violation__count__corner:nom_tt_025C_1v80,20
power__internal__total,0.00517409248277545
power__switching__total,0.009297482669353485
power__leakage__total,0.0000018622023389980313
power__total,0.014473438262939453
clock__skew__worst_hold__corner:nom_tt_025C_1v80,7.539481
clock__skew__worst_setup__corner:nom_tt_025C_1v80,8.092601
timing__hold__ws__corner:nom_tt_025C_1v80,0.223158
timing__setup__ws__corner:nom_tt_025C_1v80,4.14658
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0.0
timing__setup__wns__corner:nom_tt_025C_1v80,0.0
timing__hold_vio__count__corner:nom_tt_025C_1v80,0
timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.223158
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,6.124457
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_tt_025C_1v80,1413
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,884
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,2749
design__max_cap_violation__count__corner:nom_ss_100C_1v60,633
clock__skew__worst_hold__corner:nom_ss_100C_1v60,10.114737
clock__skew__worst_setup__corner:nom_ss_100C_1v60,11.186316
timing__hold__ws__corner:nom_ss_100C_1v60,0.365902
timing__setup__ws__corner:nom_ss_100C_1v60,0.47358
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0.0
timing__setup__wns__corner:nom_ss_100C_1v60,0.0
timing__hold_vio__count__corner:nom_ss_100C_1v60,0
timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.67361
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,0.47358
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,1413
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,60
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,2749
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,20
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,6.394931
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,6.699955
timing__hold__ws__corner:nom_ff_n40C_1v95,0.079782
timing__setup__ws__corner:nom_ff_n40C_1v95,5.485413
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.079782
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,8.43183
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,1413
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,4
design__max_fanout_violation__count__corner:min_tt_025C_1v80,2749
design__max_cap_violation__count__corner:min_tt_025C_1v80,1
clock__skew__worst_hold__corner:min_tt_025C_1v80,7.361092
clock__skew__worst_setup__corner:min_tt_025C_1v80,7.886006
timing__hold__ws__corner:min_tt_025C_1v80,0.259431
timing__setup__ws__corner:min_tt_025C_1v80,4.370804
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0.0
timing__setup__wns__corner:min_tt_025C_1v80,0.0
timing__hold_vio__count__corner:min_tt_025C_1v80,0
timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.259431
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,6.463247
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,1413
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,27
design__max_fanout_violation__count__corner:min_ss_100C_1v60,2749
design__max_cap_violation__count__corner:min_ss_100C_1v60,135
clock__skew__worst_hold__corner:min_ss_100C_1v60,9.838772
clock__skew__worst_setup__corner:min_ss_100C_1v60,10.867458
timing__hold__ws__corner:min_ss_100C_1v60,0.531116
timing__setup__ws__corner:min_ss_100C_1v60,1.108624
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0.0
timing__setup__wns__corner:min_ss_100C_1v60,0.0
timing__hold_vio__count__corner:min_ss_100C_1v60,0
timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.669473
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,1.108624
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,1413
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,4
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,2749
design__max_cap_violation__count__corner:min_ff_n40C_1v95,1
clock__skew__worst_hold__corner:min_ff_n40C_1v95,6.269701
clock__skew__worst_setup__corner:min_ff_n40C_1v95,6.555291
timing__hold__ws__corner:min_ff_n40C_1v95,0.104456
timing__setup__ws__corner:min_ff_n40C_1v95,5.689445
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0.0
timing__setup__wns__corner:min_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:min_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.104456
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,8.631856
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,1413
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,91
design__max_fanout_violation__count__corner:max_tt_025C_1v80,2749
design__max_cap_violation__count__corner:max_tt_025C_1v80,25
clock__skew__worst_hold__corner:max_tt_025C_1v80,7.697963
clock__skew__worst_setup__corner:max_tt_025C_1v80,8.276884
timing__hold__ws__corner:max_tt_025C_1v80,0.193509
timing__setup__ws__corner:max_tt_025C_1v80,3.880933
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0.0
timing__setup__wns__corner:max_tt_025C_1v80,0.0
timing__hold_vio__count__corner:max_tt_025C_1v80,0
timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.193509
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,5.939717
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,1413
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,2026
design__max_fanout_violation__count__corner:max_ss_100C_1v60,2749
design__max_cap_violation__count__corner:max_ss_100C_1v60,1521
clock__skew__worst_hold__corner:max_ss_100C_1v60,10.359847
clock__skew__worst_setup__corner:max_ss_100C_1v60,11.472188
timing__hold__ws__corner:max_ss_100C_1v60,0.210718
timing__setup__ws__corner:max_ss_100C_1v60,0.079025
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0.0
timing__setup__wns__corner:max_ss_100C_1v60,0.0
timing__hold_vio__count__corner:max_ss_100C_1v60,0
timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.67373
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
timing__setup_r2r__ws__corner:max_ss_100C_1v60,0.079025
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,1413
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,89
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2749
design__max_cap_violation__count__corner:max_ff_n40C_1v95,25
clock__skew__worst_hold__corner:max_ff_n40C_1v95,6.509506
clock__skew__worst_setup__corner:max_ff_n40C_1v95,6.83562
timing__hold__ws__corner:max_ff_n40C_1v95,0.06435
timing__setup__ws__corner:max_ff_n40C_1v95,5.224452
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.06435
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,8.318182
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count__corner:max_ff_n40C_1v95,1413
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
design__max_slew_violation__count,2026
design__max_fanout_violation__count,2749
design__max_cap_violation__count,1521
clock__skew__worst_hold,10.359847
clock__skew__worst_setup,6.555291
timing__hold__ws,0.06435
timing__setup__ws,0.079025
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0.0
timing__setup__wns,0.0
timing__hold_vio__count,0
timing__hold_r2r__ws,0.06435
timing__hold_r2r_vio__count,0
timing__setup_vio__count,0
timing__setup_r2r__ws,0.079025
timing__setup_r2r_vio__count,0
timing__unannotated_net__count,1413
timing__unannotated_net_filtered__count,0
design__xor_difference__count,0
magic__drc_error__count,55
klayout__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,3
design__lvs_net_difference__count,2
design__lvs_property_fail__count,0
design__lvs_error__count,172
design__lvs_unmatched_device__count,17
design__lvs_unmatched_net__count,71
design__lvs_unmatched_pin__count,79