2024-03-18 06:16:15 -05:00
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Metric,Value
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design__instance__count,47420
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design__instance__area,12590500
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design__instance_unmapped__count,0
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synthesis__check_error__count,0
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design__die__bbox,0.0 0.0 3165.0 4767.0
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design__core__bbox,10.12 10.88 3154.68 4754.56
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design__io,633
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design__die__area,15087600
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design__core__area,14916800
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design__instance__count__stdcell,47326
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design__instance__area__stdcell,141326
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design__instance__count__macros,94
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design__instance__area__macros,12449200
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design__instance__utilization,0.844051
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design__instance__utilization__stdcell,0.0572728
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design__power_grid_violation__count__net:vccd1,10
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design__power_grid_violation__count__net:vssd1,12
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design__power_grid_violation__count__net:vssio,143
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design__power_grid_violation__count__net:vccd,53152
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design__power_grid_violation__count__net:vdda1,804
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design__power_grid_violation__count__net:vssa2,860
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design__power_grid_violation__count__net:vssd2,800
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design__power_grid_violation__count__net:vdda2,804
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design__power_grid_violation__count__net:vddio,143
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design__power_grid_violation__count__net:vssd,1249
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design__power_grid_violation__count__net:vccd2,804
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design__power_grid_violation__count__net:vssa1,828
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design__power_grid_violation__count,59609
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timing__drv__floating__nets,34
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timing__drv__floating__pins,0
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design__instance__displacement__total,0
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design__instance__displacement__mean,0
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design__instance__displacement__max,0
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route__wirelength__estimated,1617690
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design__violations,0
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design__instance__count__setup_buffer,0
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design__instance__count__hold_buffer,0
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antenna__violating__nets,98
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antenna__violating__pins,98
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route__antenna_violation__count,98
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route__net,7904
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route__net__special,12
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route__drc_errors__iter:1,9400
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route__wirelength__iter:1,1674839
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route__drc_errors__iter:2,4061
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route__wirelength__iter:2,1673179
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route__drc_errors__iter:3,3333
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route__wirelength__iter:3,1672916
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route__drc_errors__iter:4,1150
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route__wirelength__iter:4,1675079
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route__drc_errors__iter:5,670
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route__wirelength__iter:5,1675159
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route__drc_errors__iter:6,375
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route__wirelength__iter:6,1675000
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route__drc_errors__iter:7,210
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route__wirelength__iter:7,1674925
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route__drc_errors__iter:8,199
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route__wirelength__iter:8,1674923
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route__drc_errors__iter:9,199
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route__wirelength__iter:9,1674923
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route__drc_errors__iter:10,198
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route__wirelength__iter:10,1674922
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route__drc_errors__iter:11,22
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route__wirelength__iter:11,1674959
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route__drc_errors__iter:12,1
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route__wirelength__iter:12,1674999
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route__drc_errors__iter:13,0
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route__wirelength__iter:13,1674999
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route__drc_errors,0
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route__wirelength,1674999
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route__vias,63530
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route__vias__singlecut,63530
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route__vias__multicut,0
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design__disconnected_pin__count,4
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design__critical_disconnected_pin__count,0
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route__wirelength__max,4068.8
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design__max_slew_violation__count__corner:nom_tt_025C_1v80,62
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design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2749
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design__max_cap_violation__count__corner:nom_tt_025C_1v80,20
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power__internal__total,0.00517409248277545
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power__switching__total,0.009297482669353485
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power__leakage__total,0.0000018622023389980313
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power__total,0.014473438262939453
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clock__skew__worst_hold__corner:nom_tt_025C_1v80,7.539481
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clock__skew__worst_setup__corner:nom_tt_025C_1v80,8.092601
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timing__hold__ws__corner:nom_tt_025C_1v80,0.223158
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timing__setup__ws__corner:nom_tt_025C_1v80,4.14658
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timing__hold__tns__corner:nom_tt_025C_1v80,0.0
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timing__setup__tns__corner:nom_tt_025C_1v80,0.0
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timing__hold__wns__corner:nom_tt_025C_1v80,0.0
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timing__setup__wns__corner:nom_tt_025C_1v80,0.0
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timing__hold_vio__count__corner:nom_tt_025C_1v80,0
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timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.223158
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timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
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timing__setup_vio__count__corner:nom_tt_025C_1v80,0
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timing__setup_r2r__ws__corner:nom_tt_025C_1v80,6.124457
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timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
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timing__unannotated_net__count__corner:nom_tt_025C_1v80,1413
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timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
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design__max_slew_violation__count__corner:nom_ss_100C_1v60,884
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design__max_fanout_violation__count__corner:nom_ss_100C_1v60,2749
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design__max_cap_violation__count__corner:nom_ss_100C_1v60,633
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clock__skew__worst_hold__corner:nom_ss_100C_1v60,10.114737
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clock__skew__worst_setup__corner:nom_ss_100C_1v60,11.186316
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timing__hold__ws__corner:nom_ss_100C_1v60,0.365902
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timing__setup__ws__corner:nom_ss_100C_1v60,0.47358
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timing__hold__tns__corner:nom_ss_100C_1v60,0.0
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timing__setup__tns__corner:nom_ss_100C_1v60,0.0
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timing__hold__wns__corner:nom_ss_100C_1v60,0.0
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timing__setup__wns__corner:nom_ss_100C_1v60,0.0
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timing__hold_vio__count__corner:nom_ss_100C_1v60,0
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timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.67361
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timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
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timing__setup_vio__count__corner:nom_ss_100C_1v60,0
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timing__setup_r2r__ws__corner:nom_ss_100C_1v60,0.47358
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timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
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timing__unannotated_net__count__corner:nom_ss_100C_1v60,1413
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timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
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design__max_slew_violation__count__corner:nom_ff_n40C_1v95,60
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design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,2749
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design__max_cap_violation__count__corner:nom_ff_n40C_1v95,20
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clock__skew__worst_hold__corner:nom_ff_n40C_1v95,6.394931
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clock__skew__worst_setup__corner:nom_ff_n40C_1v95,6.699955
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timing__hold__ws__corner:nom_ff_n40C_1v95,0.079782
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timing__setup__ws__corner:nom_ff_n40C_1v95,5.485413
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timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
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timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
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timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
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timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
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timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
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timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.079782
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timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
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timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
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timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,8.43183
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timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
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timing__unannotated_net__count__corner:nom_ff_n40C_1v95,1413
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timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
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design__max_slew_violation__count__corner:min_tt_025C_1v80,4
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design__max_fanout_violation__count__corner:min_tt_025C_1v80,2749
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design__max_cap_violation__count__corner:min_tt_025C_1v80,1
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clock__skew__worst_hold__corner:min_tt_025C_1v80,7.361092
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clock__skew__worst_setup__corner:min_tt_025C_1v80,7.886006
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timing__hold__ws__corner:min_tt_025C_1v80,0.259431
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timing__setup__ws__corner:min_tt_025C_1v80,4.370804
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timing__hold__tns__corner:min_tt_025C_1v80,0.0
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timing__setup__tns__corner:min_tt_025C_1v80,0.0
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timing__hold__wns__corner:min_tt_025C_1v80,0.0
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timing__setup__wns__corner:min_tt_025C_1v80,0.0
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timing__hold_vio__count__corner:min_tt_025C_1v80,0
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timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.259431
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timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
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timing__setup_vio__count__corner:min_tt_025C_1v80,0
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timing__setup_r2r__ws__corner:min_tt_025C_1v80,6.463247
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timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
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timing__unannotated_net__count__corner:min_tt_025C_1v80,1413
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timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
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design__max_slew_violation__count__corner:min_ss_100C_1v60,27
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design__max_fanout_violation__count__corner:min_ss_100C_1v60,2749
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design__max_cap_violation__count__corner:min_ss_100C_1v60,135
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clock__skew__worst_hold__corner:min_ss_100C_1v60,9.838772
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clock__skew__worst_setup__corner:min_ss_100C_1v60,10.867458
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timing__hold__ws__corner:min_ss_100C_1v60,0.531116
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timing__setup__ws__corner:min_ss_100C_1v60,1.108624
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timing__hold__tns__corner:min_ss_100C_1v60,0.0
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timing__setup__tns__corner:min_ss_100C_1v60,0.0
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timing__hold__wns__corner:min_ss_100C_1v60,0.0
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timing__setup__wns__corner:min_ss_100C_1v60,0.0
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timing__hold_vio__count__corner:min_ss_100C_1v60,0
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timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.669473
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timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
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timing__setup_vio__count__corner:min_ss_100C_1v60,0
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timing__setup_r2r__ws__corner:min_ss_100C_1v60,1.108624
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timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
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timing__unannotated_net__count__corner:min_ss_100C_1v60,1413
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timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
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design__max_slew_violation__count__corner:min_ff_n40C_1v95,4
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design__max_fanout_violation__count__corner:min_ff_n40C_1v95,2749
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design__max_cap_violation__count__corner:min_ff_n40C_1v95,1
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clock__skew__worst_hold__corner:min_ff_n40C_1v95,6.269701
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clock__skew__worst_setup__corner:min_ff_n40C_1v95,6.555291
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timing__hold__ws__corner:min_ff_n40C_1v95,0.104456
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timing__setup__ws__corner:min_ff_n40C_1v95,5.689445
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timing__hold__tns__corner:min_ff_n40C_1v95,0.0
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timing__setup__tns__corner:min_ff_n40C_1v95,0.0
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timing__hold__wns__corner:min_ff_n40C_1v95,0.0
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timing__setup__wns__corner:min_ff_n40C_1v95,0.0
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timing__hold_vio__count__corner:min_ff_n40C_1v95,0
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timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.104456
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timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
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timing__setup_vio__count__corner:min_ff_n40C_1v95,0
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timing__setup_r2r__ws__corner:min_ff_n40C_1v95,8.631856
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timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
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timing__unannotated_net__count__corner:min_ff_n40C_1v95,1413
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timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
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design__max_slew_violation__count__corner:max_tt_025C_1v80,91
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design__max_fanout_violation__count__corner:max_tt_025C_1v80,2749
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design__max_cap_violation__count__corner:max_tt_025C_1v80,25
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clock__skew__worst_hold__corner:max_tt_025C_1v80,7.697963
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clock__skew__worst_setup__corner:max_tt_025C_1v80,8.276884
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timing__hold__ws__corner:max_tt_025C_1v80,0.193509
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timing__setup__ws__corner:max_tt_025C_1v80,3.880933
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timing__hold__tns__corner:max_tt_025C_1v80,0.0
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timing__setup__tns__corner:max_tt_025C_1v80,0.0
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timing__hold__wns__corner:max_tt_025C_1v80,0.0
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timing__setup__wns__corner:max_tt_025C_1v80,0.0
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timing__hold_vio__count__corner:max_tt_025C_1v80,0
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timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.193509
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timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
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timing__setup_vio__count__corner:max_tt_025C_1v80,0
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timing__setup_r2r__ws__corner:max_tt_025C_1v80,5.939717
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timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
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timing__unannotated_net__count__corner:max_tt_025C_1v80,1413
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timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
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design__max_slew_violation__count__corner:max_ss_100C_1v60,2026
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|
|
|
|
design__max_fanout_violation__count__corner:max_ss_100C_1v60,2749
|
|
|
|
|
design__max_cap_violation__count__corner:max_ss_100C_1v60,1521
|
|
|
|
|
clock__skew__worst_hold__corner:max_ss_100C_1v60,10.359847
|
|
|
|
|
clock__skew__worst_setup__corner:max_ss_100C_1v60,11.472188
|
|
|
|
|
timing__hold__ws__corner:max_ss_100C_1v60,0.210718
|
|
|
|
|
timing__setup__ws__corner:max_ss_100C_1v60,0.079025
|
|
|
|
|
timing__hold__tns__corner:max_ss_100C_1v60,0.0
|
|
|
|
|
timing__setup__tns__corner:max_ss_100C_1v60,0.0
|
|
|
|
|
timing__hold__wns__corner:max_ss_100C_1v60,0.0
|
|
|
|
|
timing__setup__wns__corner:max_ss_100C_1v60,0.0
|
|
|
|
|
timing__hold_vio__count__corner:max_ss_100C_1v60,0
|
|
|
|
|
timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.67373
|
|
|
|
|
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
|
|
|
|
|
timing__setup_vio__count__corner:max_ss_100C_1v60,0
|
|
|
|
|
timing__setup_r2r__ws__corner:max_ss_100C_1v60,0.079025
|
|
|
|
|
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
|
|
|
|
|
timing__unannotated_net__count__corner:max_ss_100C_1v60,1413
|
|
|
|
|
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
|
|
|
|
|
design__max_slew_violation__count__corner:max_ff_n40C_1v95,89
|
|
|
|
|
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2749
|
|
|
|
|
design__max_cap_violation__count__corner:max_ff_n40C_1v95,25
|
|
|
|
|
clock__skew__worst_hold__corner:max_ff_n40C_1v95,6.509506
|
|
|
|
|
clock__skew__worst_setup__corner:max_ff_n40C_1v95,6.83562
|
|
|
|
|
timing__hold__ws__corner:max_ff_n40C_1v95,0.06435
|
|
|
|
|
timing__setup__ws__corner:max_ff_n40C_1v95,5.224452
|
|
|
|
|
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
|
|
|
|
|
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
|
|
|
|
|
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
|
|
|
|
|
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
|
|
|
|
|
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
|
|
|
|
|
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.06435
|
|
|
|
|
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
|
|
|
|
|
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
|
|
|
|
|
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,8.318182
|
|
|
|
|
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
|
|
|
|
|
timing__unannotated_net__count__corner:max_ff_n40C_1v95,1413
|
|
|
|
|
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
|
|
|
|
|
design__max_slew_violation__count,2026
|
|
|
|
|
design__max_fanout_violation__count,2749
|
|
|
|
|
design__max_cap_violation__count,1521
|
|
|
|
|
clock__skew__worst_hold,10.359847
|
|
|
|
|
clock__skew__worst_setup,6.555291
|
|
|
|
|
timing__hold__ws,0.06435
|
|
|
|
|
timing__setup__ws,0.079025
|
|
|
|
|
timing__hold__tns,0.0
|
|
|
|
|
timing__setup__tns,0.0
|
|
|
|
|
timing__hold__wns,0.0
|
|
|
|
|
timing__setup__wns,0.0
|
|
|
|
|
timing__hold_vio__count,0
|
|
|
|
|
timing__hold_r2r__ws,0.06435
|
|
|
|
|
timing__hold_r2r_vio__count,0
|
|
|
|
|
timing__setup_vio__count,0
|
|
|
|
|
timing__setup_r2r__ws,0.079025
|
|
|
|
|
timing__setup_r2r_vio__count,0
|
|
|
|
|
timing__unannotated_net__count,1413
|
|
|
|
|
timing__unannotated_net_filtered__count,0
|
|
|
|
|
design__xor_difference__count,0
|
|
|
|
|
magic__drc_error__count,55
|
|
|
|
|
klayout__drc_error__count,0
|
|
|
|
|
magic__illegal_overlap__count,0
|
|
|
|
|
design__lvs_device_difference__count,3
|
|
|
|
|
design__lvs_net_difference__count,2
|
|
|
|
|
design__lvs_property_fail__count,0
|
|
|
|
|
design__lvs_error__count,172
|
|
|
|
|
design__lvs_unmatched_device__count,17
|
|
|
|
|
design__lvs_unmatched_net__count,71
|
|
|
|
|
design__lvs_unmatched_pin__count,79
|
