caravel/verilog/dv/cocotb/tests
M0stafaRady de2f4a3707 Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
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bitbang Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
common_functions increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
cpu add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
gpio add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
hello_world add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
housekeeping/housekeeping_regs Fix housekeeping spi tests 2022-10-02 05:37:27 -07:00
irq add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
mem add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
mgmt_gpio add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
temp_partial_test add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
timer add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
uart fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00