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caravel/verilog
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M0stafaRady de2f4a3707 Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
..
dv Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
gl reharden!: gpio_control_block 2022-09-27 07:09:26 -07:00
rtl merge with caravel_redesign 2022-10-02 06:55:41 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00