| .. |
|
__uprj_analog_netlists.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
__uprj_netlists.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
__user_analog_project_wrapper.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
__user_project_wrapper.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
caravan.v
|
A handful of changes/corrections: (1) Housekeeping signal "user_clock"
|
2021-12-06 19:38:24 -05:00 |
|
caravan_netlists.v
|
Corrected an inadvertant error in caravel_netlists.v that prevents
|
2021-12-07 09:14:59 -05:00 |
|
caravan_openframe.v
|
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
|
2021-10-31 21:43:09 -04:00 |
|
caravel.v
|
A handful of changes/corrections: (1) Housekeeping signal "user_clock"
|
2021-12-06 19:38:24 -05:00 |
|
caravel_clocking.v
|
Changed the synchronized reset to occur on the clock falling edge
|
2021-12-02 14:26:59 -05:00 |
|
caravel_netlists.v
|
Corrected an inadvertant error in caravel_netlists.v that prevents
|
2021-12-07 09:14:59 -05:00 |
|
caravel_openframe.v
|
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
|
2021-10-31 21:43:09 -04:00 |
|
chip_io.v
|
A handful of changes/corrections: (1) Housekeeping signal "user_clock"
|
2021-12-06 19:38:24 -05:00 |
|
chip_io_alt.v
|
Two more changes: (1) Correction to chip_io_alt.v RTL verilog to
|
2021-12-07 17:16:44 -05:00 |
|
clock_div.v
|
Fixed one bad error in clock_div which had been done without my
|
2021-12-06 21:37:51 -05:00 |
|
defines.v
|
Update storage testbench to work with one 2K block
|
2021-11-12 17:14:21 +02:00 |
|
digital_pll.v
|
fixes for RTL testbenches with mgmt core wrapper
|
2021-12-05 10:11:10 -08:00 |
|
digital_pll_controller.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
gpio_control_block.v
|
(1) Corrected an error from a recent commit where the reset was
|
2021-11-03 23:18:36 -04:00 |
|
gpio_defaults_block.v
|
Implemented a system for setting the GPIO power-on defaults through
|
2021-10-23 17:18:30 -04:00 |
|
gpio_logic_high.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
housekeeping.v
|
This (late and invasive) change modifies the housekeeping block to
|
2021-11-29 14:23:30 -05:00 |
|
housekeeping_spi.v
|
Modified the housekeeping SPI to generate a read strobe (or rather
|
2021-10-23 22:06:24 -04:00 |
|
mgmt_protect.v
|
Revised the management protect block to include protections against
|
2021-10-27 19:36:43 -04:00 |
|
mgmt_protect_hv.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
mprj2_logic_high.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
mprj_io.v
|
A handful of changes/corrections: (1) Housekeeping signal "user_clock"
|
2021-12-06 19:38:24 -05:00 |
|
mprj_logic_high.v
|
Revised the management protect block to include protections against
|
2021-10-27 19:36:43 -04:00 |
|
pads.v
|
A handful of changes/corrections: (1) Housekeeping signal "user_clock"
|
2021-12-06 19:38:24 -05:00 |
|
ring_osc2x13.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
simple_por.v
|
Final edits to make caravel LVS clean.
|
2021-11-22 16:51:35 -05:00 |
|
spare_logic_block.v
|
Revised the spare logic block to make sure that all inputs are
|
2021-11-24 09:34:52 -05:00 |
|
user_defines.v
|
Split the layout of the GPIO defaults block into three versions, for the
|
2021-11-06 13:28:26 -04:00 |
|
user_id_programming.v
|
Implemented a system for setting the GPIO power-on defaults through
|
2021-10-23 17:18:30 -04:00 |
|
xres_buf.v
|
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
|
2021-10-31 21:43:09 -04:00 |
489bddcf98