caravel/verilog/dv/cocotb/tests
M0stafaRady 55671cded1 fix bug at bit bang tests 2022-10-15 18:10:33 -07:00
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bitbang fix bug at bit bang tests 2022-10-15 18:10:33 -07:00
common_functions update script and top level testbench for sdf 2022-10-13 04:25:14 -07:00
cpu move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
debug initial version of debug test 2022-10-15 11:40:39 -07:00
gpio fix errors for gate level 2022-10-12 10:29:56 -07:00
hello_world add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
housekeeping fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
irq fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
logicAnalyzer fix errors for gate level 2022-10-12 10:29:56 -07:00
mem Optimize and update mem tests - script is generating new linker script for the test to be all to test the whole dff or dff2 memory 2022-10-14 17:12:45 -07:00
mgmt_gpio move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
sessions/session.bitbang_spi_i.vpd.tcl add folder to store important sessions 2022-10-12 02:03:06 -07:00
spi_master fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
temp_partial_test move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
timer move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
uart fix some tests for gatelevel 2022-10-13 04:05:12 -07:00